On Thu, 21 Jul 2022 16:22:08 +0100, Frank Li <frank.li@xxxxxxx> wrote: > > > > + pos = find_first_zero_bit(&msi_data->used, IMX_MU_CHANS); > > > + if (pos < IMX_MU_CHANS) > > > + __set_bit(pos, &msi_data->used); > > > + else > > > + err = -ENOSPC; > > > + spin_unlock(&msi_data->lock); > > > + > > > + if (err) > > > + return err; > > > + > > > + err = iommu_dma_prepare_msi(info->desc, msi_data->msiir_addr + > > pos * 4); > > > > Does this HW even have an IOMMU? > > [Frank Li] we have a platform with iommu. I really wonder whether you are taking me for a ride, or whether you are completely misunderstanding what this IOMMU business is about. This is a *CPU* writing to the device to generate an MSI. CPU transactions cannot be translated by an IOMMU as they are not (surprise!) IO devices. They are in control of their own translation, contrary to devices that generate MSIs. So what sort of translation do you expect this to setup? What StreamID is getting used by the DMA framework? There is no answer to these questions because they don't make any sense. None of it makes any sense. At best, you are simply copy-pasting things from various drivers without understanding what they are all about. I suggest you stop doing that and make use of your time working out the problem rather than wasting the reviewers'. M. -- Without deviation from the norm, progress is not possible.
