On 15:11-20220719, Jérôme Neanne wrote:
> > > +&main_i2c0 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&main_i2c0_pins_default>;
> > > + clock-frequency = <400000>;
> > > + status = "okay";
> > > +
> > > + tps65219: pmic@30 {
> >
> > Am I missing something?
> > https://www.ti.com/tool/SK-AM64#design-files
> > https://www.ti.com/lit/df/sprr432/sprr432.pdf
> > Page 11:
> > I see TPS6521815 at address 0x24, nothing in 0x30?
> >
> TI provides me a preliminary spec for TPS65219 where it is stated:
> "7.3.8 I 2 C Serial Interface (SDA and SCL)
> The TPS65219 hosts a slave I2C interface that supports I2C-bus data
> transfers in Standard-mode (100 kbit/s),
> Fast-mode (400 kbit/s) and Fast-mode plus (1 Mbit/s).
> The default I2C-adress is 0x30, but can be changed if needed, e.g. for
> multi-PMIC-operation."
>
> Don't know when the spec will be released publically
>
Please do not top post.
https://www.ti.com/product/TPS65219 - the PMIC is public for sure. I am
not complaining about that.
What the I was commenting is that the AM64-SK device tree you are
modifying does'nt have the said PMIC. If this is a custom board, then
lets not upstream such a board. If another board is supposed to contain
it, lets enable the PMIC in the corresponding board.
That does'nt negate the entire series, just the device tree patches as
provided in this series is invalid - I have no intent of picking up
patches that will break everyone's am64-sk boards.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
