On Fri, 08 Jul 2022 09:56:18 -0200, Kavyasree Kotagiri wrote: > LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1 > in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins > can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on > functions being configured. > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@xxxxxxxxxxxxx> > --- > v7 -> v8: > - Changed compatible string to microchip,lan9668-flexcom. > > v6 -> v7: > - Add #address-cells, #size-cells to flx3 example. > > v5 -> v6: > - Removed spi node from flx3 example. > > v4 -> v5: > - Fixed indentations and dt-schema errors. > - No errors seen with 'make dt_binding_check'. > > v3 -> v4: > - Added else condition to allOf:if:then. > > v2 -> v3: > - Add reg property of lan966x missed in v2. > > v1 -> v2: > - Use allOf:if:then for lan966x dt properties > > .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 65 ++++++++++++++++++- > 1 file changed, 64 insertions(+), 1 deletion(-) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
