> -----Original Message-----
> From: Andrew Lunn <andrew@xxxxxxx>
> Sent: 2022年7月11日 15:02
> To: Wei Fang <wei.fang@xxxxxxx>
> Cc: davem@xxxxxxxxxxxxx; edumazet@xxxxxxxxxx; kuba@xxxxxxxxxx;
> pabeni@xxxxxxxxxx; robh+dt@xxxxxxxxxx; krzysztof.kozlowski+dt@xxxxxxxxxx;
> shawnguo@xxxxxxxxxx; s.hauer@xxxxxxxxxxxxxx; netdev@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> kernel@xxxxxxxxxxxxxx; festevam@xxxxxxxxx; dl-linux-imx
> <linux-imx@xxxxxxx>; Peng Fan <peng.fan@xxxxxxx>; Jacky Bai
> <ping.bai@xxxxxxx>; sudeep.holla@xxxxxxx;
> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; Aisheng Dong <aisheng.dong@xxxxxxx>
> Subject: [EXT] Re: [PATCH V2 3/3] arm64: dts: imx8ulp-evk: Add the fec
> support
>
> Caution: EXT Email
>
> On Mon, Jul 11, 2022 at 07:44:34PM +1000, Wei Fang wrote:
> > Enable the fec on i.MX8ULP EVK board.
> >
> > Signed-off-by: Wei Fang <wei.fang@xxxxxxx>
> > ---
> > V2 change:
> > Add clock_ext_rmii and clock_ext_ts. They are both related to EVK board.
> > ---
> > arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 57
> > +++++++++++++++++++
> > 1 file changed, 57 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > index 33e84c4e9ed8..ebce716b10e6 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > @@ -19,6 +19,21 @@ memory@80000000 {
> > device_type = "memory";
> > reg = <0x0 0x80000000 0 0x80000000>;
> > };
> > +
> > + clock_ext_rmii: clock-ext-rmii {
> > + compatible = "fixed-clock";
> > + clock-frequency = <50000000>;
> > + clock-output-names = "ext_rmii_clk";
> > + #clock-cells = <0>;
> > + };
> > +
> > + clock_ext_ts: clock-ext-ts {
> > + compatible = "fixed-clock";
> > + /* External ts clock is 50MHZ from PHY on EVK board. */
> > + clock-frequency = <50000000>;
> > + clock-output-names = "ext_ts_clk";
> > + #clock-cells = <0>;
> > + };
>
> Do you need any PHY properties to turn this clock on? Or is it strapped to be
> always on?
>
Yes, the clock is strapped to be always on, so any PHY property is not required.
> I'm surprised it is limited to Fast Ethernet. I know the Vybrid and some of the
> older SoCs are Fast Ethernet only, but i thought all the newer supported 1G?
>
> Andrew
The FEC of imx8ulp is reused from imx6ul , it supports 10/100 Mbit/s full-duplex and configurable half-duplex operation, do not support 1G.
