On 5.07.2022 21:10, Robert Marko wrote:
> APSS PLL type will be used by the IPQ8074 APSS driver for providing the
> CPU core clocks and enabling CPU Frequency scaling.
>
> This is ported from the downstream 5.4 kernel.
>
> Signed-off-by: Robert Marko <robimarko@xxxxxxxxx>
> ---
> drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++
> drivers/clk/qcom/clk-alpha-pll.h | 1 +
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 4406cf609aae..8270363ff98e 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
> [PLL_OFF_TEST_CTL_U] = 0x30,
> [PLL_OFF_TEST_CTL_U1] = 0x34,
> },
> + [CLK_ALPHA_PLL_TYPE_APSS] = {
The name is surely not correct, can somebody from qcom chime in
and suggest what it should be?
Konrad
> + [PLL_OFF_L_VAL] = 0x08,
> + [PLL_OFF_ALPHA_VAL] = 0x10,
> + [PLL_OFF_ALPHA_VAL_U] = 0xff,
> + [PLL_OFF_USER_CTL] = 0x18,
> + [PLL_OFF_USER_CTL_U] = 0xff,
> + [PLL_OFF_CONFIG_CTL] = 0x20,
> + [PLL_OFF_CONFIG_CTL_U] = 0x24,
> + [PLL_OFF_TEST_CTL] = 0x30,
> + [PLL_OFF_TEST_CTL_U] = 0x34,
> + [PLL_OFF_STATUS] = 0x28,
> + },
> };
> EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
>
> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> index 6e9907deaf30..626fdf80336d 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.h
> +++ b/drivers/clk/qcom/clk-alpha-pll.h
> @@ -18,6 +18,7 @@ enum {
> CLK_ALPHA_PLL_TYPE_AGERA,
> CLK_ALPHA_PLL_TYPE_ZONDA,
> CLK_ALPHA_PLL_TYPE_LUCID_EVO,
> + CLK_ALPHA_PLL_TYPE_APSS,
> CLK_ALPHA_PLL_TYPE_MAX,
> };
>
