Add dsi node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@xxxxxxxxxxxx>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index c4dc8777f26c..6d9164b47bd1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
+#include <dt-bindings/reset/mt8192-resets.h>
/ {
compatible = "mediatek,mt8192";
@@ -1335,6 +1336,25 @@
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
};
+ dsi0: dsi@14010000 {
+ compatible = "mediatek,mt8183-dsi";
+ reg = <0 0x14010000 0 0x1000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DSI0>,
+ <&mmsys CLK_MM_DSI_DSI0>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
+ status = "disabled";
+
+ port {
+ dsi_out: endpoint { };
+ };
+ };
+
ovl_2l2: ovl@14014000 {
compatible = "mediatek,mt8192-disp-ovl-2l";
reg = <0 0x14014000 0 0x1000>;
--
2.18.0
