On 21/06/2022 18:11, Sricharan R wrote:
> From: Varadarajan Narayanan <quic_varada@xxxxxxxxxxx>
>
> Add initial device tree support for the Qualcomm IPQ5018 SoC and
> MP03.1-C2 board.
>
> Co-developed-by: Sricharan R <quic_srichara@xxxxxxxxxxx>
> Signed-off-by: Sricharan R <quic_srichara@xxxxxxxxxxx>
> Signed-off-by: Varadarajan Narayanan <quic_varada@xxxxxxxxxxx>
Chain needs fixes.
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> .../arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts | 29 +++
> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 221 ++++++++++++++++++
> 3 files changed, 251 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
> create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index f9e6343acd03..c44e701f093c 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += ipq5018-mp03.1-c2.dtb
This does not look like in proper order.
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
> new file mode 100644
> index 000000000000..d1cd080ec3db
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> +/*
> + * IPQ5018 CP01 board device tree source
> + *
> + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "ipq5018.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ5018/AP-MP03-C2";
> + compatible = "qcom,ipq5018-mp03", "qcom,ipq5018";
> +
> + aliases {
> + serial0 = &blsp1_uart1;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&blsp1_uart1 {
> + pinctrl-0 = <&serial_1_pins>;
> + pinctrl-names = "default";
> + status = "ok";
"okay" is preferred.
> +};
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> new file mode 100644
> index 000000000000..084fb7b30dfd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -0,0 +1,221 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> +/*
> + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
> + */
> +/*
> + * IPQ5018 SoC device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
Combine these two comments.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
> +#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&intc>;
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
> + #clock-cells = <0>;
> + };
> +
> + xo: xo {
Node name: xo-clk
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
The clock is provided by board, so at least frequency should be defined
there.
> + #clock-cells = <0>;
> + };
> +
> + gen2clk0: gen2clk0 {
Keep consistent prefixes, so gen2-clk or gen2-0-clk
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + clock-output-names = "pcie20_phy0_pipe_clk";
> + };
> +
> + gen2clk1: gen2clk1 {
gen2-1-clk
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + clock-output-names = "pcie20_phy1_pipe_clk";
> + };
> +
Best regards,
Krzysztof
