The I2C pins on Intel's SoCFPGA platform are not connected to GPIOs and thus cannot be recovered by the standard GPIO method. The driver has been updated to use the "intel,socfpga-i2c" binding to reset the I2C host for error recovery. Link: https://lore.kernel.org/lkml/20220620230109.986298-1-dinguyen@xxxxxxxxxx/ Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx> --- arch/arm/boot/dts/socfpga.dtsi | 8 ++++---- arch/arm/boot/dts/socfpga_arria10.dtsi | 10 +++++----- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 10 +++++----- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 10 +++++----- 4 files changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index bfaef45bdd04..6cfbfca8b665 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -663,7 +663,7 @@ portc: gpio-controller@0 { i2c0: i2c@ffc04000 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc04000 0x1000>; resets = <&rst I2C0_RESET>; clocks = <&l4_sp_clk>; @@ -674,7 +674,7 @@ i2c0: i2c@ffc04000 { i2c1: i2c@ffc05000 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc05000 0x1000>; resets = <&rst I2C1_RESET>; clocks = <&l4_sp_clk>; @@ -685,7 +685,7 @@ i2c1: i2c@ffc05000 { i2c2: i2c@ffc06000 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc06000 0x1000>; resets = <&rst I2C2_RESET>; clocks = <&l4_sp_clk>; @@ -696,7 +696,7 @@ i2c2: i2c@ffc06000 { i2c3: i2c@ffc07000 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc07000 0x1000>; resets = <&rst I2C3_RESET>; clocks = <&l4_sp_clk>; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 4370e3cbbb4b..a8675369c07d 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -558,7 +558,7 @@ fpga_mgr: fpga-mgr@ffd03000 { i2c0: i2c@ffc02200 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc02200 0x100>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; @@ -569,7 +569,7 @@ i2c0: i2c@ffc02200 { i2c1: i2c@ffc02300 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc02300 0x100>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; @@ -580,7 +580,7 @@ i2c1: i2c@ffc02300 { i2c2: i2c@ffc02400 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc02400 0x100>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; @@ -591,7 +591,7 @@ i2c2: i2c@ffc02400 { i2c3: i2c@ffc02500 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc02500 0x100>; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; @@ -602,7 +602,7 @@ i2c3: i2c@ffc02500 { i2c4: i2c@ffc02600 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc02600 0x100>; interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; clocks = <&l4_sp_clk>; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index db771690641b..0ddfd51be590 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -244,7 +244,7 @@ portb: gpio-controller@0 { i2c0: i2c@ffc02800 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc02800 0x100>; interrupts = <0 103 4>; resets = <&rst I2C0_RESET>; @@ -255,7 +255,7 @@ i2c0: i2c@ffc02800 { i2c1: i2c@ffc02900 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc02900 0x100>; interrupts = <0 104 4>; resets = <&rst I2C1_RESET>; @@ -266,8 +266,8 @@ i2c1: i2c@ffc02900 { i2c2: i2c@ffc02a00 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; reg = <0xffc02a00 0x100>; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; interrupts = <0 105 4>; resets = <&rst I2C2_RESET>; clocks = <&clkmgr STRATIX10_L4_SP_CLK>; @@ -277,7 +277,7 @@ i2c2: i2c@ffc02a00 { i2c3: i2c@ffc02b00 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc02b00 0x100>; interrupts = <0 106 4>; resets = <&rst I2C3_RESET>; @@ -288,7 +288,7 @@ i2c3: i2c@ffc02b00 { i2c4: i2c@ffc02c00 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc02c00 0x100>; interrupts = <0 107 4>; resets = <&rst I2C4_RESET>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 7bbec8aafa62..17e733a48b9d 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -248,7 +248,7 @@ portb: gpio-controller@0 { i2c0: i2c@ffc02800 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc02800 0x100>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; resets = <&rst I2C0_RESET>; @@ -259,7 +259,7 @@ i2c0: i2c@ffc02800 { i2c1: i2c@ffc02900 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc02900 0x100>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; resets = <&rst I2C1_RESET>; @@ -270,7 +270,7 @@ i2c1: i2c@ffc02900 { i2c2: i2c@ffc02a00 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc02a00 0x100>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; resets = <&rst I2C2_RESET>; @@ -281,7 +281,7 @@ i2c2: i2c@ffc02a00 { i2c3: i2c@ffc02b00 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc02b00 0x100>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; resets = <&rst I2C3_RESET>; @@ -292,7 +292,7 @@ i2c3: i2c@ffc02b00 { i2c4: i2c@ffc02c00 { #address-cells = <1>; #size-cells = <0>; - compatible = "snps,designware-i2c"; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; reg = <0xffc02c00 0x100>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; resets = <&rst I2C4_RESET>; -- 2.25.1
