On 13/06/2022 05:47, Piyush Mehta wrote: > Add a new DT quirk to dwc3 core to resolved issue of CRC failed error. > On the resume path, U3/U2 exit controller fails to send proper CRC > checksum in CRC5 field. As result Transaction Error is generated. > Enabling bit 10 of GUCTL1 will correct this problem. > > When this bit is set to '1', the UTMI/ULPI opmode will be changed to > "normal" along with HS terminations after EOR. > This option is to support certain legacy UTMI/ULPI PHYs. > > Signed-off-by: Piyush Mehta <piyush.mehta@xxxxxxxxxx> > --- > Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml > index d41265ba8ce2..36fa87df57a9 100644 > --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml > +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml > @@ -234,6 +234,12 @@ properties: > avoid -EPROTO errors with usbhid on some devices (Hikey 970). > type: boolean > > + snps,enable_guctl1_resume_quirk: No underscores in properties, use hyphens. > + description: > + Set if we enable quirk for fixing improper crc generation after resume > + from suspend. Please describe actual issue, hardware property, not driver behavior. In the description and property name. This could be something like "snps,missing-src-after-resume" (or anything better). Best regards, Krzysztof
