On Fri, Jun 10, 2022 at 11:17:55AM +0300, Serge Semin wrote:
> Synopsys AHCI SATA controller is mainly compatible with the generic AHCI
> SATA controller except a few peculiarities and the platform environment
> requirements. In particular it can have one or two reference clocks to
> feed up its AXI/AHB interface and SATA PHYs domain and at least one reset
> control for the application clock domain. In addition to that the DMA
> interface of each port can be tuned up to work with the predefined maximum
> data chunk size. Note unlike generic AHCI controller DWC AHCI can't have
> more than 8 ports. All of that is reflected in the new DWC AHCI SATA
> device DT binding.
>
> Note the DWC AHCI SATA controller DT-schema has been created in a way so
> to be reused for the vendor-specific DT-schemas (see for example the
> "snps,dwc-ahci" compatible string binding). One of which we are about to
> introduce.
>
> Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
>
> ---
>
> Changelog v2:
> - Replace min/max constraints of the snps,{tx,rx}-ts-max property with
> enum [ 1, 2, 4, ..., 1024 ]. (@Rob)
>
> Changelog v4:
> - Decrease the "additionalProperties" property identation otherwise it's
> percieved as the node property instead of the key one. (@Rob)
> - Use the ahci-port properties definition from the AHCI common schema
> in order to extend it with DWC AHCI SATA port properties. (@Rob)
> - Remove the Hannes' rb tag since the patch content has changed.
> ---
> .../bindings/ata/ahci-platform.yaml | 8 --
> .../bindings/ata/snps,dwc-ahci.yaml | 129 ++++++++++++++++++
> 2 files changed, 129 insertions(+), 8 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
>
> diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
> index e19cf9828e68..7dc2a2e8f598 100644
> --- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml
> +++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
> @@ -30,8 +30,6 @@ select:
> - marvell,armada-3700-ahci
> - marvell,armada-8k-ahci
> - marvell,berlin2q-ahci
> - - snps,dwc-ahci
> - - snps,spear-ahci
> required:
> - compatible
>
> @@ -48,17 +46,11 @@ properties:
> - marvell,berlin2-ahci
> - marvell,berlin2q-ahci
> - const: generic-ahci
> - - items:
> - - enum:
> - - rockchip,rk3568-dwc-ahci
> - - const: snps,dwc-ahci
> - enum:
> - cavium,octeon-7130-ahci
> - hisilicon,hisi-ahci
> - ibm,476gtr-ahci
> - marvell,armada-3700-ahci
> - - snps,dwc-ahci
> - - snps,spear-ahci
>
> reg:
> minItems: 1
> diff --git a/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
> new file mode 100644
> index 000000000000..af78f6c9b857
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
> @@ -0,0 +1,129 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Synopsys DWC AHCI SATA controller
> +
> +maintainers:
> + - Serge Semin <fancer.lancer@xxxxxxxxx>
> +
> +description:
> + This document defines device tree bindings for the Synopsys DWC
> + implementation of the AHCI SATA controller.
> +
> +allOf:
> + - $ref: ahci-common.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - description: Synopsys AHCI SATA-compatible devices
> + contains:
> + const: snps,dwc-ahci
> + - description: SPEAr1340 AHCI SATA device
> + const: snps,spear-ahci
> + - description: Rockhip RK3568 ahci controller
> + const: rockchip,rk3568-dwc-ahci
This is never true because there is a fallback. We should keep what we
had before.
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + description:
> + Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock
> + and embedded PHYs reference clock together with vendor-specific set
> + of clocks.
> + minItems: 1
> + maxItems: 4
> +
> + clock-names:
> + contains:
> + anyOf:
> + - description: Application AXI/AHB BIU clock source
> + enum:
> + - aclk
> + - sata
> + - description: SATA Ports reference clock
> + enum:
> + - ref
> + - sata_ref
> +
> + resets:
> + description:
> + At least basic core and application clock domains reset is normally
> + supported by the DWC AHCI SATA controller. Some platform specific
> + clocks can be also specified though.
s/clocks/resets/ ?
This allows any number of resets which isn't great. I think this schema
should just be the 'simple' cases where there's only 1 reset and 1
clock (or how many the DWC block actually has if you have that info).
More complicated cases get there own schema.
> +
> + reset-names:
> + contains:
> + description: Core and application clock domains reset control
> + const: arst
> +
> +patternProperties:
> + "^sata-port@[0-9a-e]$":
> + $ref: '#/$defs/dwc-ahci-port'
> +
> + unevaluatedProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +unevaluatedProperties: false
> +
> +$defs:
> + dwc-ahci-port:
> + $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port
> +
> + properties:
> + reg:
> + minimum: 0
> + maximum: 7
> +
> + snps,tx-ts-max:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Maximal size of Tx DMA transactions in FIFO words
> + enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]
> +
> + snps,rx-ts-max:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Maximal size of Rx DMA transactions in FIFO words
> + enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/ata/ahci.h>
> +
> + sata@122f0000 {
> + compatible = "snps,dwc-ahci";
> + reg = <0x122F0000 0x1ff>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&clock1>, <&clock2>;
> + clock-names = "aclk", "ref";
> +
> + phys = <&sata_phy>;
> + phy-names = "sata-phy";
> +
> + ports-implemented = <0x1>;
> +
> + sata-port@0 {
> + reg = <0>;
> +
> + hba-port-cap = <HBA_PORT_FBSCP>;
> +
> + snps,tx-ts-max = <512>;
> + snps,rx-ts-max = <512>;
> + };
> + };
> +...
> --
> 2.35.1
>
>
