Indeed in accordance with what is implemented in the AHCI platform driver
and the way the AHCI DT nodes are defined in the DT files we can add the
next AHCI DT properties constraints: AHCI CSR ID is fixed to 'ahci', PHY
name is fixed to 'sata-phy', AHCI controller can't have more than 32 ports
by design, AHCI controller can have up to 32 IRQ lines.
Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
Reviewed-by: Hannes Reinecke <hare@xxxxxxx>
---
Changelog v2:
- This is a new patch created after rebasing v1 onto the 5.18-rc3 kernel.
Changelog v4:
- Fix spelling: 'imeplemtned' and 'paltform' in the patch log. (@Hannes)
- Add the interrupts property constraints. (@Rob)
- Add forgotten '---' patchlog-changelog separator. (@Sergei)
---
.../devicetree/bindings/ata/ahci-common.yaml | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/ata/ahci-common.yaml b/Documentation/devicetree/bindings/ata/ahci-common.yaml
index e89bda3b62cc..12a97b56226f 100644
--- a/Documentation/devicetree/bindings/ata/ahci-common.yaml
+++ b/Documentation/devicetree/bindings/ata/ahci-common.yaml
@@ -31,12 +31,16 @@ properties:
reg-names:
description: CSR space IDs
+ contains:
+ const: ahci
interrupts:
description:
Generic AHCI state change interrupt. Can be implemented either as a
single line attached to the controller or as a set of the signals
indicating the particular port events.
+ minItems: 1
+ maxItems: 32
ahci-supply:
description: Power regulator for AHCI controller
@@ -52,14 +56,13 @@ properties:
maxItems: 1
phy-names:
- maxItems: 1
+ const: sata-phy
ports-implemented:
$ref: '/schemas/types.yaml#/definitions/uint32'
description:
Mask that indicates which ports the HBA supports. Useful if PI is not
programmed by the BIOS, which is true for some embedded SoC's.
- maximum: 0x1f
patternProperties:
"^sata-port@[0-9a-f]+$":
@@ -80,8 +83,12 @@ $defs:
properties:
reg:
- description: AHCI SATA port identifier
- maxItems: 1
+ description:
+ AHCI SATA port identifier. By design AHCI controller can't have
+ more than 32 ports due to the CAP.NP fields and PI register size
+ constraints.
+ minimum: 0
+ maximum: 31
phys:
description: Individual AHCI SATA port PHY
@@ -89,7 +96,7 @@ $defs:
phy-names:
description: AHCI SATA port PHY ID
- maxItems: 1
+ const: sata-phy
target-supply:
description: Power regulator for SATA port target device
--
2.35.1
