Re: [PATCH 2/2] arm64: dts: mediatek: mt8195: add pwm node

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Il 31/05/22 13:45, Fabien Parent ha scritto:
MT8195's PWM IP has 4 PWM blocks.

Signed-off-by: Fabien Parent <fparent@xxxxxxxxxxxx>

I've verified that the binding is actually right - and it is, the MT8183
data is a perfect match with MT8195.

In any case, there are at least a few MT8195 boards on which the PWM controller
is not used (only the disp-pwm one is used), so please set this node as disabled
by default, after which, you get my:

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>

---
  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++
  1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index d076a376bdcc..366543f27a99 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -367,6 +367,21 @@ pwrap: pwrap@10024000 {
  			assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
  		};
+ pwm0: pwm@10048000 {
+			compatible = "mediatek,mt8195-pwm",
+				     "mediatek,mt8183-pwm";
+			reg = <0 0x10048000 0 0x1000>;
+			#pwm-cells = <2>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_PWM_H>,
+				 <&infracfg_ao CLK_INFRA_AO_PWM>,
+				 <&infracfg_ao CLK_INFRA_AO_PWM1>,
+				 <&infracfg_ao CLK_INFRA_AO_PWM2>,
+				 <&infracfg_ao CLK_INFRA_AO_PWM3>,
+				 <&infracfg_ao CLK_INFRA_AO_PWM4>;
+			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
+				      "pwm4";
+		};
+
  		scp_adsp: clock-controller@10720000 {
  			compatible = "mediatek,mt8195-scp_adsp";
  			reg = <0 0x10720000 0 0x1000>;






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