On 02/06/2022 16:11, wen.ping.teh@xxxxxxxxx wrote:
> From: Teh Wen Ping <wen.ping.teh@xxxxxxxxx>
>
> Add Stratix 10 Software Virtual Platform device tree
>
> Signed-off-by: Teh Wen Ping <wen.ping.teh@xxxxxxxxx>
> ---
>
> changes in v2:
> -remove indentation before GPL
> -change root compatible to "altr,socfpga-stratix10"
> -remove bootargs
> -move clock-frequency to label
> -remove l2-cache
> -remove no longer exist authors from commit message
>
> arch/arm64/Kconfig.platforms | 3 +-
> arch/arm64/boot/dts/altera/Makefile | 3 +-
> .../dts/altera/socfpga_stratix10_swvp.dts | 117 ++++++++++++++++++
> 3 files changed, 121 insertions(+), 2 deletions(-)
> create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index de9a18d3026f..48abe5dafaae 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -249,7 +249,8 @@ config ARCH_INTEL_SOCFPGA
> bool "Intel's SoCFPGA ARMv8 Families"
> help
> This enables support for Intel's SoCFPGA ARMv8 families:
> - Stratix 10 (ex. Altera), Agilex and eASIC N5X.
> + Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform,
> + Agilex and eASIC N5X.
>
> config ARCH_SYNQUACER
> bool "Socionext SynQuacer SoC Family"
> diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile
> index 4db83fbeb115..1bf0c472f6b4 100644
> --- a/arch/arm64/boot/dts/altera/Makefile
> +++ b/arch/arm64/boot/dts/altera/Makefile
> @@ -1,3 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0-only
> dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \
> - socfpga_stratix10_socdk_nand.dtb
> + socfpga_stratix10_socdk_nand.dtb \
> + socfpga_stratix10_swvp.dtb
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts
> new file mode 100644
> index 000000000000..93fa5091a6c3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2022, Intel Corporation
> + */
> +
> +#include "socfpga_stratix10.dtsi"
> +
> +/ {
> + model = "SOCFPGA Stratix 10 SWVP";
> + compatible = "altr,socfpga-stratix10";
You cannot use someone else's compatible. You need your own and then
also you need to document it. Check existing sources for examples.
Documentation/devicetree/bindings/arm/altera.yaml
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> +
> + timer0 = &timer0;
> + timer1 = &timer1;
> + timer2 = &timer2;
> + timer3 = &timer3;
> +
> + ethernet0 = &gmac0;
> + ethernet1 = &gmac1;
> + ethernet2 = &gmac2;
> + };
> +
> + chosen {
> + stdout-path = "serial1:115200n8";
> + linux,initrd-start = <0x10000000>;
> + linux,initrd-end = <0x125c8324>;
Best regards,
Krzysztof
