On Mon, May 23, 2022 at 09:18:33PM +0300, Dmitry Baryshkov wrote:
> On some of Qualcomm platforms each group of 32 MSI vectors is routed to the
> separate GIC interrupt. Implement support for such configurations by
> parsing "msi0" ... "msiN" interrupts and attaching them to the chained
> handler.
>
> Note, that if DT doesn't list an array of MSI interrupts and uses single
> "msi" IRQ, the driver will limit the amount of supported MSI vectors
> accordingly (to 32).
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
> .../pci/controller/dwc/pcie-designware-host.c | 61 +++++++++++++++++--
> 1 file changed, 57 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index a076abe6611c..98a57249ecaf 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -288,6 +288,47 @@ static void dw_pcie_msi_init(struct pcie_port *pp)
> dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
> }
>
> +static const char * const split_msi_names[] = {
> + "msi0", "msi1", "msi2", "msi3",
> + "msi4", "msi5", "msi6", "msi7",
> +};
> +
> +static int dw_pcie_parse_split_msi_irq(struct pcie_port *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct device *dev = pci->dev;
> + struct platform_device *pdev = to_platform_device(dev);
> + int irq;
> + u32 ctrl, max_vectors;
> +
> + /* Parse as many IRQs as described in the devicetree. */
> + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
> + irq = platform_get_irq_byname_optional(pdev, split_msi_names[ctrl]);
I'd do this instead:
char *msi_name = "msiX";
msi_name[3] = '0' + ctrl;
Otherwise,
Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
