The div4 clocks in Exynos7885 were mistakenly set to have the wrong parents making them and their children display 2x the actual clockrate. This in turn lead to the DTSI getting the wrong clocks for UART, since that's the configuration it worked properly with. This was noticed by Sam Protsenko [1] but since it worked this way and not the other way around, I didn't think much of it. [1] https://lore.kernel.org/linux-samsung-soc/CAPLW+4k3Vmg0W0jVsTChHTG8+eeg=5QF+actz1Tk0vNV9w-y-A@xxxxxxxxxxxxxx/ David Virag (2): clk: samsung: exynos7885: Correct "div4" clock parents arm64: dts: exynos: Correct UART clocks on Exynos7885 arch/arm64/boot/dts/exynos/exynos7885.dtsi | 12 ++++++------ drivers/clk/samsung/clk-exynos7885.c | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) -- 2.35.1
