Hi Prabhakar, > Subject: Re: [PATCH v4 0/7] Renesas RZ/G2L IRQC support > > On Wed, May 18, 2022 at 10:10 PM Andy Shevchenko > <andy.shevchenko@xxxxxxxxx> wrote: > > > > On Wed, May 18, 2022 at 9:29 PM Lad Prabhakar > > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote: > > > > > > Hi All, > > > > > > The RZ/G2L Interrupt Controller is a front-end for the GIC found on > > > Renesas RZ/G2L SoC's with below pins: > > > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI > > > interrupts > > > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a > > > maximum of only 32 can be mapped to 32 GIC SPI interrupts, > > > - NMI edge select. > > > > > > > _____________ > > > | GIC > | > > > | > ________ | > > > ____________ | | > | | > > > NMI --------------------------------->| | SPI0-479 | | GIC- > 600| | > > > _______ | |------------>| > | | > > > | | | | PPI16-31 | | > | | > > > | | IRQ0-IRQ7 | IRQC |------------>| > | | > > > P0_P48_4 --->| GPIO |---------------->| | | > |________| | > > > | |GPIOINT0-122 | | | > | > > > | |---------------->| TINT0-31 | | > | > > > |______| |__________| > |____________| > > > > > > The proposed patches add hierarchical IRQ domain, one in IRQC driver > > > and another in pinctrl driver. Upon interrupt requests map the > > > interrupt to GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC > > > SPI, this mapping is handled by the pinctrl and IRQC driver. > > > > Where is the explanation on why valid_mask can't be used instead? > > > The .valid_mask option is one time setting One question, if it is one time setting, Is it possible to use .valid mask to invalidate invalid gpio lines?(ie, currently gpio range is 392, but there is only 123 GPIOs present in the SoC, not sure this call back can be used to invalidate the non-supported GPIOS??). Cheers, Biju but what I need is something > dynamic i.e. out of 392 GPIO pins any 32 can be used as an interrupt pin. > Also with this patch we also save on memory here [0]. , > > Andy Shevchenko
