Hi Geert,
Thank you for the review.
On Tue, May 10, 2022 at 3:02 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> On Thu, May 5, 2022 at 9:32 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote:
> > Renesas RZ/Five SoC has almost the same clock structure compared to the
> > Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just
> > ammend the RZ/Five CPG clock and reset definitions.
>
> amend
>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> > --- a/include/dt-bindings/clock/r9a07g043-cpg.h
> > +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> > @@ -108,6 +108,15 @@
> > #define R9A07G043_ADC_ADCLK 76
> > #define R9A07G043_ADC_PCLK 77
> > #define R9A07G043_TSU_PCLK 78
> > +#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */
>
> While NCEPLDM_DM_CLK is listed in the clock list spreadsheet, its
> control bit is not documented.
>
> > +#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */
> > +#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */
>
> While NCEPLDM_TCK is listed in the clock list spreadsheet, its
> control bit is not documented.
>
I have got the feedback for the above, NCEPLDM_DM_CLK and NCEPLDM_TCK
clocks cannot be stopped as a result there are no register bits for it
in the HW manual (clock spreadsheet will be updated). I will drop this
and send a v2 including your RB.
Cheers,
Prabhakar
> The rest LGTM, so with the above clarified
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
