On Wed, 2022-05-18 at 12:09 +0200, Hans Verkuil wrote: > Hi Moudy, > > On 5/12/22 11:23, Moudy Ho wrote: > > This patch adds DT binding documents for Media Data Path 3 (MDP3) > > a unit in multimedia system combined with several components and > > used for scaling and color format convert. > > > > Signed-off-by: Moudy Ho <moudy.ho@xxxxxxxxxxxx> > > --- > > .../bindings/media/mediatek,mdp3-rdma.yaml | 85 > > +++++++++++++++++++ > > .../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++++++++++ > > .../bindings/media/mediatek,mdp3-wrot.yaml | 70 +++++++++++++++ > > .../bindings/soc/mediatek/mediatek,ccorr.yaml | 58 +++++++++++++ > > .../bindings/soc/mediatek/mediatek,wdma.yaml | 71 > > ++++++++++++++++ > > This changes bindings in two subsystems in a single patch. I would > recommend splitting > this up. Besides, the subject specifically says "MDP3 components", so > having other > components in this patch is confusing. > > The soc bindings can either go through the soc subsystem or through > the media > subsystem, but then I need Acked-by from the maintainer. > Hello Hans, There is something wrong for Moudy's mediatek mail server, so I help him to reply this mail to prevent the mismatch of discussion between Moudy and you. Moudy will split the bindings under ./soc/mediatek into a separate patch in the next version. > > 5 files changed, 349 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml > > create mode 100644 > > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml > > create mode 100644 > > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml > > create mode 100644 > > Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml > > Why is this part of soc/mediatek instead of media? CSC is typically a > media operation. > > I'm not saying it is wrong, but it's a bit odd. Apologies if this was > asked before. > > Regards, > > Hans > The purpose of this path change is to allow Mediatek's MDP and DRM to share the same binding, and the same concept as the previous patch listed below: https://patchwork.kernel.org/project/linux-mediatek/patch/20220315061031.21642-4-moudy.ho@xxxxxxxxxxxx/ The current path is preliminary and subject to review. Please let me know if there is a proper one. BRs, Rex > > create mode 100644 > > Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3- > > rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3- > > rdma.yaml > > new file mode 100644 > > index 000000000000..4fe704e476dc > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3- > > rdma.yaml > > @@ -0,0 +1,85 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uZLfyeWNg$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uYTQJNp6g$ > > > > + > > +title: Mediatek Read Direct Memory Access > > + > > +maintainers: > > + - Matthias Brugger <matthias.bgg@xxxxxxxxx> > > + - Ping-Hsun Wu <ping-hsun.wu@xxxxxxxxxxxx> > > + > > +description: | > > + Mediatek Read Direct Memory Access(RDMA) component used to do > > read DMA. > > + It contains one line buffer to store the sufficient pixel data, > > and > > + must be siblings to the central MMSYS_CONFIG node. > > + For a description of the MMSYS_CONFIG binding, see > > + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.ya > > ml > > + for details. > > + > > +properties: > > + compatible: > > + items: > > + - const: mediatek,mt8183-mdp3-rdma > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + description: The register of client driver can be configured > > by gce with > > + 4 arguments defined in this property. Each GCE subsys id is > > mapping to > > + a client defined in the header include/dt- > > bindings/gce/<chip>-gce.h. > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: RDMA clock > > + - description: RSZ clock > > + > > + iommus: > > + maxItems: 1 > > + > > + mboxes: > > + items: > > + - description: used for 1st data pipe from RDMA > > + - description: used for 2nd data pipe from RDMA > > + > > +required: > > + - compatible > > + - reg > > + - mediatek,gce-client-reg > > + - power-domains > > + - clocks > > + - iommus > > + - mboxes > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt8183-clk.h> > > + #include <dt-bindings/gce/mt8183-gce.h> > > + #include <dt-bindings/power/mt8183-power.h> > > + #include <dt-bindings/memory/mt8183-larb-port.h> > > + > > + mdp3_rdma0: mdp3-rdma0@14001000 { > > + compatible = "mediatek,mt8183-mdp3-rdma"; > > + reg = <0x14001000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 > > 0x1000>; > > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_MDP_RDMA0>, > > + <&mmsys CLK_MM_MDP_RSZ1>; > > + iommus = <&iommu>; > > + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, > > + <&gce 21 CMDQ_THR_PRIO_LOWEST>; > > + }; > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3- > > rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3- > > rsz.yaml > > new file mode 100644 > > index 000000000000..7b566fbec3c0 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3- > > rsz.yaml > > @@ -0,0 +1,65 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uYLnzDDrw$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uYTQJNp6g$ > > > > + > > +title: Mediatek Resizer > > + > > +maintainers: > > + - Matthias Brugger <matthias.bgg@xxxxxxxxx> > > + - Ping-Hsun Wu <ping-hsun.wu@xxxxxxxxxxxx> > > + > > +description: | > > + One of Media Data Path 3 (MDP3) components used to do frame > > resizing. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8183-mdp3-rsz > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + description: The register of client driver can be configured > > by gce with > > + 4 arguments defined in this property. Each GCE subsys id is > > mapping to > > + a client defined in the header include/dt- > > bindings/gce/<chip>-gce.h. > > + > > + clocks: > > + minItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - mediatek,gce-client-reg > > + - clocks > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt8183-clk.h> > > + #include <dt-bindings/gce/mt8183-gce.h> > > + > > + mdp3_rsz0: mdp3-rsz0@14003000 { > > + compatible = "mediatek,mt8183-mdp3-rsz"; > > + reg = <0x14003000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 > > 0x1000>; > > + clocks = <&mmsys CLK_MM_MDP_RSZ0>; > > + }; > > + > > + mdp3_rsz1: mdp3-rsz1@14004000 { > > + compatible = "mediatek,mt8183-mdp3-rsz"; > > + reg = <0x14004000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 > > 0x1000>; > > + clocks = <&mmsys CLK_MM_MDP_RSZ1>; > > + }; > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3- > > wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3- > > wrot.yaml > > new file mode 100644 > > index 000000000000..5481d4e43315 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3- > > wrot.yaml > > @@ -0,0 +1,70 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uY3xwuR8Q$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uYTQJNp6g$ > > > > + > > +title: Mediatek Write DMA with Rotation > > + > > +maintainers: > > + - Matthias Brugger <matthias.bgg@xxxxxxxxx> > > + - Ping-Hsun Wu <ping-hsun.wu@xxxxxxxxxxxx> > > + > > +description: | > > + One of Media Data Path 3 (MDP3) components used to write DMA > > with frame rotation. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8183-mdp3-wrot > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + description: The register of client driver can be configured > > by gce with > > + 4 arguments defined in this property. Each GCE subsys id is > > mapping to > > + a client defined in the header include/dt- > > bindings/gce/<chip>-gce.h. > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + minItems: 1 > > + > > + iommus: > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - mediatek,gce-client-reg > > + - power-domains > > + - clocks > > + - iommus > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt8183-clk.h> > > + #include <dt-bindings/gce/mt8183-gce.h> > > + #include <dt-bindings/power/mt8183-power.h> > > + #include <dt-bindings/memory/mt8183-larb-port.h> > > + > > + mdp3_wrot0: mdp3-wrot0@14005000 { > > + compatible = "mediatek,mt8183-mdp3-wrot"; > > + reg = <0x14005000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 > > 0x1000>; > > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_MDP_WROT0>; > > + iommus = <&iommu>; > > + }; > > diff --git > > a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam > > l > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam > > l > > new file mode 100644 > > index 000000000000..20d02cb4ad0a > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam > > l > > @@ -0,0 +1,58 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1ua8l4S1Sg$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uYTQJNp6g$ > > > > + > > +title: Mediatek color correction > > + > > +maintainers: > > + - Matthias Brugger <matthias.bgg@xxxxxxxxx> > > + - Ping-Hsun Wu <ping-hsun.wu@xxxxxxxxxxxx> > > + > > +description: | > > + Mediatek color correction with 3X3 matrix. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8183-mdp3-ccorr > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + description: The register of client driver can be configured > > by gce with > > + 4 arguments defined in this property. Each GCE subsys id is > > mapping to > > + a client defined in the header include/dt- > > bindings/gce/<chip>-gce.h. > > + > > + clocks: > > + minItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - mediatek,gce-client-reg > > + - clocks > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt8183-clk.h> > > + #include <dt-bindings/gce/mt8183-gce.h> > > + > > + mdp3_ccorr: mdp3-ccorr@1401c000 { > > + compatible = "mediatek,mt8183-mdp3-ccorr"; > > + reg = <0x1401c000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 > > 0x1000>; > > + clocks = <&mmsys CLK_MM_MDP_CCORR>; > > + }; > > diff --git > > a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > new file mode 100644 > > index 000000000000..102d9e163139 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > @@ -0,0 +1,71 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uZKK4h1GQ$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2ZNvgvI6qeg4eNprUQ48EiE4ubRcbyNYwEQQ7zr4Nyzt6FxZ0Zs8e8ae-Puy-aLskT378PmjEAnr6ceJ1uYTQJNp6g$ > > > > + > > +title: Mediatek Write Direct Memory Access > > + > > +maintainers: > > + - Matthias Brugger <matthias.bgg@xxxxxxxxx> > > + - Ping-Hsun Wu <ping-hsun.wu@xxxxxxxxxxxx> > > + > > +description: | > > + Mediatek Write Direct Memory Access(WDMA) component used to > > write > > + the data into DMA. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8183-mdp3-wdma > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + description: The register of client driver can be configured > > by gce with > > + 4 arguments defined in this property. Each GCE subsys id is > > mapping to > > + a client defined in the header include/dt- > > bindings/gce/<chip>-gce.h. > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + minItems: 1 > > + > > + iommus: > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - mediatek,gce-client-reg > > + - power-domains > > + - clocks > > + - iommus > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt8183-clk.h> > > + #include <dt-bindings/gce/mt8183-gce.h> > > + #include <dt-bindings/power/mt8183-power.h> > > + #include <dt-bindings/memory/mt8183-larb-port.h> > > + > > + mdp3_wdma: mdp3-wdma@14006000 { > > + compatible = "mediatek,mt8183-mdp3-wdma"; > > + reg = <0x14006000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 > > 0x1000>; > > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_MDP_WDMA0>; > > + iommus = <&iommu>; > > + };
