On Wed, May 04, 2022 at 02:27:22PM +0200, Robert Foss wrote: > Add device tree bindings for graphics clock controller for > Qualcomm Technology Inc's SM8350 SoCs. > > Signed-off-by: Robert Foss <robert.foss@xxxxxxxxxx> > Reviewed-by: Dmitry Baryshkov <dmityr.baryshkov@xxxxxxxxxx> > --- > .../devicetree/bindings/clock/qcom,gpucc.yaml | 2 + > include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 +++++++++++++++++++ > 2 files changed, 54 insertions(+) > create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml > index 9ebcb1943b0a..4090cc7ea2ae 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml > @@ -20,6 +20,7 @@ description: | > dt-bindings/clock/qcom,gpucc-sm6350.h > dt-bindings/clock/qcom,gpucc-sm8150.h > dt-bindings/clock/qcom,gpucc-sm8250.h > + dt-bindings/clock/qcom,gpucc-sm8350.h > > properties: > compatible: > @@ -31,6 +32,7 @@ properties: > - qcom,sm6350-gpucc > - qcom,sm8150-gpucc > - qcom,sm8250-gpucc > + - qcom,sm8350-gpucc > > clocks: > items: > diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h > new file mode 100644 > index 000000000000..d2294e0d527e > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h > @@ -0,0 +1,52 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ QCom reviewed and approved the license on this, right? Dual license. > +/* > + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H > +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H > + > +/* GPU_CC clocks */ > +#define GPU_CC_AHB_CLK 0 > +#define GPU_CC_CB_CLK 1 > +#define GPU_CC_CRC_AHB_CLK 2 > +#define GPU_CC_CX_APB_CLK 3 > +#define GPU_CC_CX_GMU_CLK 4 > +#define GPU_CC_CX_QDSS_AT_CLK 5 > +#define GPU_CC_CX_QDSS_TRIG_CLK 6 > +#define GPU_CC_CX_QDSS_TSCTR_CLK 7 > +#define GPU_CC_CX_SNOC_DVM_CLK 8 > +#define GPU_CC_CXO_AON_CLK 9 > +#define GPU_CC_CXO_CLK 10 > +#define GPU_CC_FREQ_MEASURE_CLK 11 > +#define GPU_CC_GMU_CLK_SRC 12 > +#define GPU_CC_GX_GMU_CLK 13 > +#define GPU_CC_GX_QDSS_TSCTR_CLK 14 > +#define GPU_CC_GX_VSENSE_CLK 15 > +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 > +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17 > +#define GPU_CC_HUB_AON_CLK 18 > +#define GPU_CC_HUB_CLK_SRC 19 > +#define GPU_CC_HUB_CX_INT_CLK 20 > +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21 > +#define GPU_CC_MND1X_0_GFX3D_CLK 22 > +#define GPU_CC_MND1X_1_GFX3D_CLK 23 > +#define GPU_CC_PLL0 24 > +#define GPU_CC_PLL1 25 > +#define GPU_CC_SLEEP_CLK 26 > + > +/* GPU_CC resets */ > +#define GPUCC_GPU_CC_ACD_BCR 0 > +#define GPUCC_GPU_CC_CB_BCR 1 > +#define GPUCC_GPU_CC_CX_BCR 2 > +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 > +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 > +#define GPUCC_GPU_CC_GMU_BCR 5 > +#define GPUCC_GPU_CC_GX_BCR 6 > +#define GPUCC_GPU_CC_XO_BCR 7 > + > +/* GPU_CC GDSCRs */ > +#define GPU_CX_GDSC 0 > +#define GPU_GX_GDSC 1 > + > +#endif > -- > 2.34.1 > >
