Add the bindings for the clock drivers of the MediaTek Helio X10 MT6795 SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> --- .../arm/mediatek/mediatek,mt6795-clock.yaml | 67 +++++++++++++++++ .../mediatek/mediatek,mt6795-sys-clock.yaml | 73 +++++++++++++++++++ 2 files changed, 140 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml new file mode 100644 index 000000000000..b7d96d0ed867 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt6795-clock.yaml#"; +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; + +title: MediaTek Functional Clock Controller for MT6795 + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> + - Chun-Jie Chen <chun-jie.chen@xxxxxxxxxxxx> + +description: | + The clock architecture in MediaTek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The devices provide clock gate control in different IP blocks. + +properties: + compatible: + items: + - enum: + - mediatek,mt6795-mfgcfg + - mediatek,mt6795-vdecsys + - mediatek,mt6795-vencsys + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@13000000 { + compatible = "mediatek,mt6795-mfgcfg"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@16000000 { + compatible = "mediatek,mt6795-vdecsys"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@18000000 { + compatible = "mediatek,mt6795-vdecsys"; + reg = <0 0x18000000 0 0x1000>; + #clock-cells = <1>; + }; + }; + + diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml new file mode 100644 index 000000000000..389dd8e245ac --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt6795-sys-clock.yaml#"; +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; + +title: MediaTek System Clock Controller for MT6795 + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> + - Chun-Jie Chen <chun-jie.chen@xxxxxxxxxxxx> + +description: + The Mediatek system clock controller provides various clocks and system configuration + like reset and bus protection on MT6795. + +properties: + compatible: + items: + - enum: + - mediatek,mt6795-apmixedsys + - mediatek,mt6795-infracfg + - mediatek,mt6795-pericfg + - mediatek,mt6795-topckgen + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt6795-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: power-controller@10001000 { + compatible = "mediatek,mt6795-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + } + + pericfg: power-controller@10003000 { + compatible = "mediatek,mt6795-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apmixedsys: clock-controller@10209000 { + compatible = "mediatek,mt6795-apmixedsys", "syscon"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + }; -- 2.35.1
