Hi Anup and Heiko, The CBO specification says: """ 2.7. Software Discovery The initial set of CMO extensions requires the following information to be discovered by software: • The size of the cache block for management and prefetch instructions • The size of the cache block for zero instructions """ Therefore we should add riscv,cboz-block-size as well, or? Additionally, should we add riscv,cbop-block-size as well or rename riscv,cbom-block-size into riscv,cbom-cbop-block-size to reflect that this size is also used for prefetch instructions? BR Christoph On Thu, May 12, 2022 at 6:18 AM Anup Patel <anup@xxxxxxxxxxxxxx> wrote: > > On Thu, May 12, 2022 at 3:11 AM Heiko Stuebner <heiko@xxxxxxxxx> wrote: > > > > The Zicbom operates on a block-size defined for the cpu-core, > > which does not necessarily match other cache-sizes used. > > > > So add the necessary property for the system to know the core's > > block-size. > > > > Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx> > > Looks good to me. > > Reviewed-by: Anup Patel <anup@xxxxxxxxxxxxxx> > > Regards, > Anup > > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index d632ac76532e..b179bfd155a3 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -63,6 +63,13 @@ properties: > > - riscv,sv48 > > - riscv,none > > > > + riscv,cbom-block-size: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + description: > > + Blocksize in bytes for the Zicbom cache operations. The block > > + size is a property of the core itself and does not necessarily > > + match other software defined cache sizes. > > + > > riscv,isa: > > description: > > Identifies the specific RISC-V instruction set architecture > > -- > > 2.35.1 > >
