Hey Matthias,
On 5/11/22 10:29 PM, Matthias Kaehlcke wrote:
Hi Sibi,
On Wed, May 11, 2022 at 01:49:22PM +0530, Sibi Sankar wrote:
Add MSS PIL loading bindings for SC7280 SoCs.
Signed-off-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
There is already a binding for 'qcom,sc7280-mss-pil' in
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt. Shouldn't
the entries from that file be deleted?
v3:
* Re-ordered clock list, fixed pdc_sync typo [Rob/Matthias]
.../bindings/remoteproc/qcom,sc7280-mss-pil.yaml | 261 +++++++++++++++++++++
1 file changed, 261 insertions(+)
create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml
new file mode 100644
index 000000000000..2f95bfd7b3eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml
@@ -0,0 +1,261 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-mss-pil.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SC7280 MSS Peripheral Image Loader
+
+maintainers:
+ - Sibi Sankar <quic_sibis@xxxxxxxxxxx>
+
+description:
+ This document defines the binding for a component that loads and boots firmware
+ on the Qualcomm Technology Inc. SC7280 Modem Hexagon Core.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sc7280-mss-pil
+
+ reg:
+ items:
+ - description: MSS QDSP6 registers
+ - description: RMB registers
+
+ reg-names:
+ items:
+ - const: qdsp6
+ - const: rmb
+
+ iommus:
+ items:
+ - description: MSA Stream 1
+ - description: MSA Stream 2
+
+ interconnects:
+ items:
+ - description: Path leading to system memory
+
+ interrupts:
+ items:
+ - description: Watchdog interrupt
+ - description: Fatal interrupt
+ - description: Ready interrupt
+ - description: Handover interrupt
+ - description: Stop acknowledge interrupt
+ - description: Shutdown acknowledge interrupt
+
+ interrupt-names:
+ items:
+ - const: wdog
+ - const: fatal
+ - const: ready
+ - const: handover
+ - const: stop-ack
+ - const: shutdown-ack
The existing binding (qcom,q6v5.txt) also has:
- interrupts-extended:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the interrupts that match interrupt-names
That's covered implicitly by 'interrupts' I suppose?
Yeah ^^ was discussed before during the sc7280 wpss patch series. Rob
said the tooling handles both the same way.
https://lore.kernel.org/lkml/CAL_Jsq+khyhbwJ5-GPZ5ZGkY4nX_obq4t92Z0V6sZH3Oyj4Fow@xxxxxxxxxxxxxx/
+
+ clocks:
+ items:
+ - description: GCC MSS IFACE clock
+ - description: GCC MSS OFFLINE clock
+ - description: GCC MSS SNOC_AXI clock
+ - description: RPMH PKA clock
+ - description: RPMH XO clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: offline
+ - const: snoc_axi
+ - const: pka
+ - const: xo
+
+ power-domains:
+ items:
+ - description: CX power domain
+ - description: MSS power domain
+
+ power-domain-names:
+ items:
+ - const: cx
+ - const: mss
+
+ resets:
+ items:
+ - description: AOSS restart
+ - description: PDC reset
+
+ reset-names:
+ items:
+ - const: mss_restart
+ - const: pdc_reset
+
+ memory-region:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: Phandle reference to the reserved-memory for the MBA region followed
+ by the modem region.
+
+ firmware-name:
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ The name of the firmware which should be loaded for this remote
+ processor.
+
+ qcom,halt-regs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Phandle reference to a syscon representing TCSR followed by the
+ four offsets within syscon for q6, modem, nc and vq6 halt registers.
+
+ qcom,ext-regs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Two phandle references to syscons representing TCSR_REG and TCSR register
+ space followed by the two offsets within the syscon to force_clk_en/rscc_disable
+ and axim1_clk_off/crypto_clk_off registers respectively.
+
+ qcom,qaccept-regs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Phandle reference to a syscon representing TCSR followed by the
+ three offsets within syscon for mdm, cx and axi qaccept registers.
+
+ qcom,qmp:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Reference to the AOSS side-channel message RAM.
+
+ qcom,smem-states:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: States used by the AP to signal the Hexagon core
+ items:
+ - description: Stop the modem
+
+ qcom,smem-state-names:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: The names of the state bits used for SMP2P output
+ const: stop
+
+ glink-edge:
+ type: object
+ description: |
+ Qualcomm G-Link subnode which represents communication edge, channels
+ and devices related to the DSP.
+
+ properties:
+ interrupts:
+ items:
+ - description: IRQ from MSS to GLINK
+
+ mboxes:
+ items:
+ - description: Mailbox for communication between APPS and MSS
+
+ label:
+ description: The names of the state bits used for SMP2P output
+ items:
+ - const: modem
+
+ qcom,remote-pid:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: ID of the shared memory used by GLINK for communication with MSS
+
+ required:
+ - interrupts
+ - mboxes
+ - label
+ - qcom,remote-pid
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - iommus
+ - interconnects
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - power-domains
+ - power-domain-names
+ - resets
+ - reset-names
+ - qcom,halt-regs
+ - qcom,ext-regs
+ - qcom,qaccept-regs
+ - memory-region
+ - qcom,qmp
'qcom,qmp' is marked as 'optional' in qcom,q6v5.txt
Yeah even though we were forced to mark/implement it as optional in the
original bindings file/driver (since it was a single bindings file
covering all the SoCs), it is functionally required for sc7280 mss to
reach xo-shutdown.
-Sibi
