On 09/05/2022 10:49, Kavyasree Kotagiri wrote: > This adds DT bindings documentation for lan966 flexcom > mux controller. > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@xxxxxxxxxxxxx> > --- > .../mux/microchip,lan966-flx-mux.yaml | 51 +++++++++++++++++++ > 1 file changed, 51 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml > > diff --git a/Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml b/Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml > new file mode 100644 > index 000000000000..63147a2e8f3a > --- /dev/null > +++ b/Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml > @@ -0,0 +1,51 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mux/microchip,lan966-flx-mux.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip Lan966 Flexcom multiplexer bindings s/bindings// > + > +maintainers: > + - Kavyasree Kotagiri <kavyasree.kotagiri@xxxxxxxxxxxxx> > + > +description: |+ No need for |+ > + The Microchip Lan966 have 5 Flexcoms. Each flexcom has 2 chip-selects > + when operating in USART and SPI modes. > + Each chip select of each flexcom can be mapped to 21 flexcom shared pins. > + Define register offset and pin number to map a flexcom chip-select > + to flexcom shared pin. > + > +allOf: > + - $ref: /schemas/mux/mux-controller.yaml# > + > +properties: > + compatible: > + const: microchip,lan966-flx-mux > + > + reg: > + maxItems: 1 > + > + '#mux-control-cells': > + const: 1 > + > + mux-offset-pin: > + description: an array of register offset and flexcom shared pin(0-20). This does not look like generic property, so you need vendor prefix and type/ref. > + > +required: > + - compatible > + - reg > + - '#mux-control-cells' > + - mux-offset-pin > + > +additionalProperties: false > + > +examples: > + - | > + mux: mux-controller@e2004168 { > + compatible = "microchip,lan966-flx-mux"; > + reg = <0xe2004168 0x8>; > + #mux-control-cells = <1>; > + mux-offset-pin = <0x18 9>; /* 0: flx3 cs0 offset, pin-9 */ > + }; > +... Best regards, Krzysztof
