From: Denys Drozdov <denys.drozdov@xxxxxxxxxxx>
Move all Atmel nodes from the board-level into the main module-level
device tree and prepare the device trees for use with Atmel MXT device
tree overlays. Also, add required pinmux groups.
The common scheme for pin groups in touch screen overlays is as follows:
- pinctrl_atmel_conn - SODIMM 106/107 pins for INT/RST signals (default)
- pinctrl_atmel_adap - SODIMM 28/30 pins for INT/RST signals.
Signed-off-by: Denys Drozdov <denys.drozdov@xxxxxxxxxxx>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@xxxxxxxxxxx>
---
Changes in v3:
- Fixed reset GPIO polarity in-line with the following upstream commit:
feedaacdadfc ("Input: atmel_mxt_ts - fix up inverted RESET handler")
- Fixed comment using more common SODIMM followed by number naming.
Changes in v2:
- Fixed pinctrl node names as suggested by Shawn.
.../arm/boot/dts/imx6ull-colibri-nonwifi.dtsi | 4 +-
arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 4 +-
arch/arm/boot/dts/imx6ull-colibri.dtsi | 39 +++++++++++++------
3 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
index 95a11b8bcbdb..5e55a6c820bc 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
@@ -15,10 +15,10 @@ memory@80000000 {
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
- &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>;
+ &pinctrl_gpio4 &pinctrl_gpio6 &pinctrl_gpio7>;
};
&iomuxc_snvs {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2 &pinctrl_snvs_gpio3>;
+ pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>;
};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
index 9f1e38282bee..6e8ddb07e11d 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
@@ -26,13 +26,13 @@ &cpu0 {
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
- &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio7>;
+ &pinctrl_gpio4 &pinctrl_gpio7>;
};
&iomuxc_snvs {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2>;
+ pinctrl-0 = <&pinctrl_snvs_gpio1>;
};
&usdhc2 {
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 7cd912df5d19..c89b209be316 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -124,6 +124,19 @@ &i2c1 {
pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ /* Atmel maxtouch controller */
+ atmel_mxt_ts: touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_atmel_conn>;
+ reg = <0x4a>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */
+ status = "disabled";
+ };
};
&i2c2 {
@@ -241,6 +254,20 @@ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */
>;
};
+ pinctrl_atmel_adap: atmeladapgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */
+ MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */
+ >;
+ };
+
+ pinctrl_atmel_conn: atmelconngrp {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
+ >;
+ };
+
pinctrl_can_int: canint-grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */
@@ -347,12 +374,6 @@ MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */
>;
};
- pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
- fsl,pins = <
- MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */
- >;
- };
-
pinctrl_gpio6: gpio6-grp { /* Wifi pins */
fsl,pins = <
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */
@@ -606,12 +627,6 @@ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */
>;
};
- pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
- fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
- >;
- };
-
pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
fsl,pins = <
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */
--
2.35.1
