On Thu, May 05, 2022 at 04:54:06PM +0300, Dmitry Baryshkov wrote: > On Qualcomm platforms each group of 32 MSI vectors is routed to the > separate GIC interrupt. Document mapping of additional interrupts. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 45 ++++++++++++++++++- > 1 file changed, 44 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 0b69b12b849e..fd3290e0e220 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -43,11 +43,20 @@ properties: > maxItems: 5 > > interrupts: > - maxItems: 1 > + minItems: 1 > + maxItems: 8 > > interrupt-names: > + minItems: 1 > items: > - const: msi > + - const: msi2 Is 2 from some documentation or you made up. If the latter, software folks start numbering at 0, not 1. :) I wouldn't care, but I think this may become common. > + - const: msi3 > + - const: msi4 > + - const: msi5 > + - const: msi6 > + - const: msi7 > + - const: msi8
