On Fri 29 Apr 11:10 CDT 2022, Doug Anderson wrote:
> Hi,
>
> On Thu, Apr 28, 2022 at 5:02 PM Matthias Kaehlcke <mka@xxxxxxxxxxxx> wrote:
> >
> > On Wed, Apr 27, 2022 at 10:39:43PM +0530, Srinivasa Rao Mandadapu wrote:
> > > Add LPASS LPI pinctrl properties, which are required for Audio
> > > functionality on herobrine based platforms of rev5+
> > > (aka CRD 3.0/3.1) boards.
> > >
> > > Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@xxxxxxxxxxx>
> > > Co-developed-by: Venkata Prasad Potturu <quic_potturu@xxxxxxxxxxx>
> > > Signed-off-by: Venkata Prasad Potturu <quic_potturu@xxxxxxxxxxx>
> >
> > I'm not super firm in pinctrl territory, a few maybe silly questions
> > below.
> >
> > > arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 84 +++++++++++++++++++++++
> > > 1 file changed, 84 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
> > > index deaea3a..dfc42df 100644
> > > --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
> > > +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
> > > @@ -111,6 +111,90 @@ ap_ts_pen_1v8: &i2c13 {
> > > * - If a pin is not hooked up on Qcard, it gets no name.
> > > */
> > >
> > > +&lpass_dmic01 {
> > > + clk {
> > > + drive-strength = <8>;
> > > + };
>
> Ugh, I've been distracted and I hadn't realized we were back to the
> two-level syntax. Definitely not my favorite for all the reasons I
> talked about [1]. I guess you took Bjorn's silence to my response to
> mean that you should switch back to this way? :(
>
> Bjorn: can you clarify?
>
I didn't think through the fact that &mi2s0_state was specified in the
.dtsi and as such will be partially be overridden by the baord dts.
I do prefer the two level style and describing full "states", but as you
say whenever we provide something that will have to be overwritten it's
suboptimal.
As such, I think your flattened model is preferred in this case - but it
makes me dislike the partial definition between the dtsi and dts even
more (but I don't have any better suggestion).
Regards,
Bjorn
> [1] https://lore.kernel.org/r/CAD=FV=VicFiX6QkBksZs1KLwJ5x4eCte6j5RWOBPN+WwiXm2Cw@xxxxxxxxxxxxxx/
>
> > > +};
> > > +
> > > +&lpass_dmic01_sleep {
> > > + clk {
> > > + drive-strength = <2>;
> >
> > Does the drive strength really matter in the sleep state, is the SoC actively
> > driving the pin?
>
> My understanding is that if a pin is left as an output in sleep state
> that there is a slight benefit to switching it to drive-strength 2.
>
>
> > > + bias-disable;
> >
> > What should this be in active/default state? If I understand correctly
> > after a transition from 'sleep' to 'default' this setting will remain,
> > since the default config doesn't specify a setting for bias.
>
> Your understanding matches mine but I haven't tested it and I remember
> sometimes being surprised in this corner of pinmux before. I think
> it's better to put the bias in the default state if it should be that
> way all the time, or have a bias in both the default and sleep state
> if they need to be different.
