On 2022-05-03 12:55, Phil Edworthy wrote:
Some SoCs use a gated clock for the timer and the means to reset the
timer.
Hence add these as optional.
The architecture is crystal clear on the subject: the counter
is in an always-on domain. Why should this be visible to SW?
Also, reseting the counter breaks the guaranteed monotonicity
we rely on.
Worse case, this belongs to the boot firmware, not the kernel,
and I don't think this should be described in the DT.
M.
Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
---
.../devicetree/bindings/timer/arm,arch_timer.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git
a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
index df8ce87fd54b..20cd90fc7015 100644
--- a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
+++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
@@ -64,6 +64,13 @@ properties:
CNTFRQ on all CPUs to a uniform correct value. Use of this
property is
strongly discouraged; fix your firmware unless absolutely
impossible.
+ clocks:
+ description: Optional clock for the timer.
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
always-on:
type: boolean
description: If present, the timer is powered through an always-on
power
--
Jazz is not dead. It just smells funny...
