Hi Aradhya,
On 14:38-20220427, Aradhya Bhatia wrote:
> Add DT node for the Display SubSystem on the am62x soc in cbass_main.
> The DSS IP on this soc is compatible with the one on the am65x soc.
>
> The DSS supports one each of video pipeline (vid) and video-lite
> pipeline (vidl1). It outputs OLDI signals on one video port (vp1) and
> DPI signals on another (vp2). The video ports are connected to the
> pipelines via 2 identical overlay managers (ovr1 and ovr2).
>
> Signed-off-by: Aradhya Bhatia <a-bhatia1@xxxxxx>
> ---
> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 30 ++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> index eec8dae65e7c..ff21efa4ffad 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> @@ -515,6 +515,36 @@ cpts@3d000 {
> };
> };
>
> + dss: dss@30200000 {
> + compatible = "ti,am65x-dss";
> +
> + reg = <0x00 0x30200000 0x00 0x1000>, /* common */
> + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
> + <0x00 0x30206000 0x00 0x1000>, /* vid */
> + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
> + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
> + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
> + <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */
> +
> + reg-names = "common", "vidl1", "vid",
> + "ovr1", "ovr2", "vp1", "vp2";
> +
> + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
> +
> + clocks = <&k3_clks 186 4>,
> + <&k3_clks 186 0>,
> + <&k3_clks 186 2>;
> +
> + clock-names = "fck", "vp1", "vp2";
> +
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +
> + dss_ports: ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
address and size cells are added in dts as well, its not required here
> + };
> + };
> +
> hwspinlock: spinlock@2a000000 {
> compatible = "ti,am64-hwspinlock";
> reg = <0x00 0x2a000000 0x00 0x1000>;
> --
> 2.36.0
>
