On Thu, Apr 28, 2022 at 09:11:58AM +0000, Zev Weiss wrote:
> On Fri, Apr 22, 2022 at 11:30:07AM PDT, Jonathan Neuschäfer wrote:
> >In the WPCM450 SoC, the clocks for each timer can be gated individually.
> >To prevent the timer 1 clock from being gated, enable it explicitly.
> >
> >Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@xxxxxxx>
> >---
> > drivers/clocksource/timer-npcm7xx.c | 14 +++++++++++++-
> > 1 file changed, 13 insertions(+), 1 deletion(-)
> >
> >diff --git a/drivers/clocksource/timer-npcm7xx.c b/drivers/clocksource/timer-npcm7xx.c
> >index a00520cbb660a..974269b6b0c36 100644
> >--- a/drivers/clocksource/timer-npcm7xx.c
> >+++ b/drivers/clocksource/timer-npcm7xx.c
> >@@ -188,17 +188,29 @@ static void __init npcm7xx_clocksource_init(void)
> >
> > static int __init npcm7xx_timer_init(struct device_node *np)
> > {
> >+ struct clk *clk;
> > int ret;
> >
> > ret = timer_of_init(np, &npcm7xx_to);
> >- if (ret)
> >+ if (ret) {
> >+ pr_warn("timer_of_init failed: %d\n", ret);
>
> This seems like a somewhat opaque message to emit, especially given this
> file's lack of a pr_fmt() definition -- maybe add a %pOF so it's
> slightly easier to trace back to the device it stems from?
Now that I look at this code again, I think I should just drop the
pr_warn entirely, since I didn't mention it in the description, and it's
unrelated to enabling the clock.
> > return ret;
> >+ }
> >
> > /* Clock input is divided by PRESCALE + 1 before it is fed */
> > /* to the counter */
> > npcm7xx_to.of_clk.rate = npcm7xx_to.of_clk.rate /
> > (NPCM7XX_Tx_MIN_PRESCALE + 1);
> >
> >+ /* Enable the clock for timer1, if it exists */
> >+ clk = of_clk_get(np, 1);
> >+ if (clk) {
> >+ if (!IS_ERR(clk))
> >+ clk_prepare_enable(clk);
> >+ else
> >+ pr_warn("Failed to get clock for timer1: %pe", clk);
>
> Likewise here (though to a slightly lesser extent).
I'll add %pOF here.
Thanks,
Jonathan
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