Hello,
On Sat, Apr 23, 2022 at 11:56:42AM +0200, Krzysztof Kozlowski wrote:
> On 22/04/2022 20:30, Jonathan Neuschäfer wrote:
> > The Nuvoton WPCM450 SoC has a combined clock and reset controller.
> > Add a devicetree binding for it, as well as definitions for the bit
> > numbers used by it.
> >
> > Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@xxxxxxx>
> > ---
>
> Thank you for your patch. There is something to discuss/improve.
>
> > .../bindings/clock/nuvoton,wpcm450-clk.yaml | 74 +++++++++++++++++++
> > .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++++++++++++++++
> > 2 files changed, 141 insertions(+)
[...]
> > +title: Nuvoton WPCM450 clock controller binding
>
> s/binding//
Will change.
> > +description:
> > + This binding describes the clock controller of the Nuvoton WPCM450 SoC, which
> > + supplies clocks and resets to the rest of the chip.
>
> s/This binding describes//
>
> Just describe the hardware.
Ok.
> > + clk: clock-controller@b0000200 {
> > + reg = <0xb0000200 0x100>;
> > + compatible = "nuvoton,wpcm450-clk";
> > + clocks = <&refclk>;
> > + clock-names = "refclk";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + serial@b8000000 {
> > + compatible = "nuvoton,wpcm450-uart";
> > + reg = <0xb8000000 0x20>;
> > + reg-shift = <2>;
> > + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk WPCM450_CLK_UART0>;
> > + };
>
> Skip the consumer example, it's obvious/trivial/duplicating.
Ok.
> > +#ifndef _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H
> > +#define _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H
> > +
> > +/* Clocks based on CLKEN bits */
> > +#define WPCM450_CLK_FIU 0
[...]
> > +/* Other clocks */
> > +#define WPCM450_CLK_USBPHY 32
> > +
> > +#define WPCM450_NUM_CLKS 33
> > +
> > +/* Resets based on IPSRST bits */
>
> All these defines should be in second header in dt-bindings/reset/...
(my reply is further down in the thread)
>
> > +#define WPCM450_RESET_FIU 0
Thanks,
Jonathan
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