On Sat, Apr 9, 2022 at 9:56 PM Sander Vanheule <sander@xxxxxxxxxxxxx> wrote: > On SoCs with multiple cores, it is possible that the GPIO interrupt > controller supports assigning specific pins to one or more cores. > > IRQ balancing can be performed on a line-by-line basis if the parent > interrupt is routed to all available cores, which is the default upon > initialisation. > > Signed-off-by: Sander Vanheule <sander@xxxxxxxxxxxxx> That sounds complicated. Sounds like something the IRQ maintainer (Marc Z) should have a quick look at. Yours, Linus Walleij
