On 06/04/22 10:28 pm, Rahul T R wrote: > From: Tomi Valkeinen <tomi.valkeinen@xxxxxx> > > Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP > 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper. > > A slight irregularity in the bindings is the DPTX PHY register block, > which is in the MHDP IP, but is needed and mapped by the PHY. > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen@xxxxxx> > Signed-off-by: Rahul T R <r-ravikumar@xxxxxx> > --- > arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 65 +++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > index db0669985e42..11426c25a09d 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > @@ -5,6 +5,7 @@ > * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ > */ > #include <dt-bindings/phy/phy.h> > +#include <dt-bindings/phy/phy-ti.h> > #include <dt-bindings/mux/mux.h> > #include <dt-bindings/mux/ti-serdes.h> > > @@ -789,6 +790,47 @@ > #size-cells = <2>; > }; > > + serdes_wiz4: wiz@5050000 { > + compatible = "ti,am64-wiz-10g"; > + #address-cells = <1>; > + #size-cells = <1>; > + power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; > + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; > + assigned-clocks = <&k3_clks 297 9>; > + assigned-clock-parents = <&k3_clks 297 10>; > + assigned-clock-rates = <19200000>; > + num-lanes = <4>; > + #reset-cells = <1>; > + #clock-cells = <1>; > + ranges = <0x5050000 0x0 0x5050000 0x10000>, > + <0xa030a00 0x0 0xa030a00 0x40>; Add leading 0s to align to 8 digit value like rest of the file: ranges = <0x05050000 0x00 0x05050000 0x10000>, <0x0a030a00 0x00 0x0a030a00 0x40>; > + > + serdes4: serdes@5050000 { > + /* > + * Note: we also map DPTX PHY registers as the Torrent > + * needs to manage those. > + */ > + compatible = "ti,j721e-serdes-10g"; > + reg = <0x5050000 0x10000>, > + <0xa030a00 0x40>; /* DPTX PHY */ Same here. > + reg-names = "torrent_phy", "dptx_phy"; > + > + resets = <&serdes_wiz4 0>; > + reset-names = "torrent_reset"; > + clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; > + clock-names = "refclk"; > + assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, > + <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, > + <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; > + assigned-clock-parents = <&k3_clks 297 9>, > + <&k3_clks 297 9>, > + <&k3_clks 297 9>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > main_uart0: serial@2800000 { > compatible = "ti,j721e-uart", "ti,am654-uart"; > reg = <0x00 0x02800000 0x00 0x100>; > @@ -1267,6 +1309,29 @@ > }; > }; > > + mhdp: dp-bridge@a000000 { > + compatible = "ti,j721e-mhdp8546"; > + /* > + * Note: we do not map DPTX PHY area, as that is handled by > + * the PHY driver. > + */ > + reg = <0x0 0xa000000 0x0 0x30a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ > + <0x0 0x4f40000 0x0 0x20>; /* DSS_EDP0_INTG_CFG_VP */ Please use 0x00 as rest of the file like: reg = <0x00 0x0a000000 0x00 0x30a00>, <0x00 0x04f40000 0x00 0x20>; > + reg-names = "mhdptx", "j721e-intg"; > + > + clocks = <&k3_clks 151 36>; > + > + interrupt-parent = <&gic500>; > + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; > + > + power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; > + > + dp0_ports: ports { > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > dss: dss@4a00000 { > compatible = "ti,j721e-dss"; > reg =
