On Wed, Apr 13, 2022 at 03:21:29PM +0800, allen-kh.cheng wrote:
> Hi Nícolas,
>
> On Tue, 2022-04-12 at 19:08 -0400, Nícolas F. R. A. Prado wrote:
> > Hi Allen,
> >
> > On Fri, Apr 08, 2022 at 06:41:24PM +0800, Allen-KH Cheng wrote:
> > > Add vcodec lat and core nodes for mt8192 SoC.
> > >
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@xxxxxxxxxxxx>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@xxxxxxxxxxxxx>
> > > ---
> > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60
> > > ++++++++++++++++++++++++
> > > 1 file changed, 60 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 18a58239d6f1..c7f4b2fbb315 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -1120,6 +1120,66 @@
> > > power-domains = <&spm
> > > MT8192_POWER_DOMAIN_ISP2>;
> > > };
> > >
> > > + vcodec_dec: vcodec-dec@16000000 {
> > > + compatible = "mediatek,mt8192-vcodec-dec";
> > > + reg = <0 0x16000000 0 0x1000>;
> > > + mediatek,scp = <&scp>;
> > > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0
> > > 0xfff00000>;
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> >
> > The dt-binding says address-cells and size-cells should be 1. Then
> > most of the
> > extra 0s can be dropped from ranges and the children's regs.
> >
> > Other than that,
> >
> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx>
> >
> > Thanks,
> > Nícolas
> >
>
> I have checked the description in mediatek,vcodec-subdev-decoder.yaml
>
> address-cells and size-cells are two after the below commit is merged.
>
> media: mediatek,vcodec: Fix addressing cell sizes
> linux/kernel/git/next/linux-next.git
> commit/id=a50e431bbc6fc5768ed26be5fab5b149b7b8b1fe
Hi Allen,
yes, you're right. I missed that commit, sorry. This patch is perfectly fine
as it is then.
Thanks,
Nícolas
>
> Correct me if I got this wrong.
>
> Thanks,
> Allen
>
> > > + ranges = <0 0 0 0x16000000 0 0x26000>;
> > > +
> > > + vcodec_lat: vcodec-lat@10000 {
> > > + compatible = "mediatek,mtk-vcodec-lat";
> > > + reg = <0x0 0x10000 0 0x800>;
> > > + interrupts = <GIC_SPI 426
> > > IRQ_TYPE_LEVEL_HIGH 0>;
> > > + iommus = <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > > + <&vdecsys_soc
> > > CLK_VDEC_SOC_VDEC>,
> > > + <&vdecsys_soc
> > > CLK_VDEC_SOC_LAT>,
> > > + <&vdecsys_soc
> > > CLK_VDEC_SOC_LARB1>,
> > > + <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + clock-names = "sel", "soc-vdec", "soc-
> > > lat", "vdec", "top";
> > > + assigned-clocks = <&topckgen
> > > CLK_TOP_VDEC_SEL>;
> > > + assigned-clock-parents = <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + power-domains = <&spm
> > > MT8192_POWER_DOMAIN_VDEC>;
> > > + };
> > > +
> > > + vcodec_core: vcodec-core@25000 {
> > > + compatible = "mediatek,mtk-vcodec-
> > > core";
> > > + reg = <0 0x25000 0 0x1000>;
> > > + interrupts = <GIC_SPI 425
> > > IRQ_TYPE_LEVEL_HIGH 0>;
> > > + iommus = <&iommu0
> > > M4U_PORT_L4_VDEC_MC_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_UFO_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PP_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_TILE_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_VLD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_VLD2_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > > + <&vdecsys CLK_VDEC_VDEC>,
> > > + <&vdecsys CLK_VDEC_LAT>,
> > > + <&vdecsys CLK_VDEC_LARB1>,
> > > + <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + clock-names = "sel", "soc-vdec", "soc-
> > > lat", "vdec", "top";
> > > + assigned-clocks = <&topckgen
> > > CLK_TOP_VDEC_SEL>;
> > > + assigned-clock-parents = <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + power-domains = <&spm
> > > MT8192_POWER_DOMAIN_VDEC2>;
> > > + };
> > > + };
> > > +
> > > larb5: larb@1600d000 {
> > > compatible = "mediatek,mt8192-smi-larb";
> > > reg = <0 0x1600d000 0 0x1000>;
> > > --
> > > 2.18.0
> > >
> > >
>
