On 12/04/2022 12:10, Krzysztof Kozlowski wrote:
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>
> On 12/04/2022 14:04, Conor.Dooley@xxxxxxxxxxxxx wrote:
>> On 12/04/2022 11:47, Krzysztof Kozlowski wrote:
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>>>
>>> On 11/04/2022 10:59, Conor Dooley wrote:
>>>> The RTC reference and MSSPLL were previously not documented or defined,
>>>> as they were unused. Add their defines to the PolarFire SoC header.
>>>>
>>>> Fixes: 2145bb687e3f ("dt-bindings: clk: microchip: Add Microchip PolarFire host binding")
>>>> Reviewed-by: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx>
>>>> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
>>>> ---
>>>> include/dt-bindings/clock/microchip,mpfs-clock.h | 5 ++++-
>>>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h
>>>> index 73f2a9324857..3cba46b9191f 100644
>>>> --- a/include/dt-bindings/clock/microchip,mpfs-clock.h
>>>> +++ b/include/dt-bindings/clock/microchip,mpfs-clock.h
>>>> @@ -1,15 +1,18 @@
>>>> /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>>>> /*
>>>> * Daire McNamara,<daire.mcnamara@xxxxxxxxxxxxx>
>>>> - * Copyright (C) 2020 Microchip Technology Inc. All rights reserved.
>>>> + * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
>>>> */
>>>>
>>>> #ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
>>>> #define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
>>>>
>>>> +#define CLK_MSSPLL 34
>>>
>>> You have some weird order here. Shouldn't it be under CLK_RTCREF?
>>
>> Yeah numerically weirdly ordered - I grouped the clocks by type:
>> MSSPLL is a pll, CPU/AXI/AHB/RTC are all dividers & the rest are on/off
>> toggles. I'd've prefered to have renumbered the whole list, but that
>> didn't feel like a good idea.
>>
>> Additionally MSSPLL is the source for CLK_{CPI,AXI,AHB} so I put it at
>> the top. I have no particular preference, so if you want them reordered
>> so that MSSPLL is under RTCREF just say the word :)
>
> Hm, are these in the same clock controller (device, not driver)? If yes,
> then please order them numerically. Pretty often one binding header have
> IDs for several clock controllers, so then it's a different case.
Not *quite* sure what you mean by device. There is only one SoC that
this header applies to, but in the actual design the MSSPLL is in one
block, the RTC divider in another and CLK_CPU -> CLK_CFM in a third.
