The uart9 was previously mistakenly called uart2. Fix this.
Signed-off-by: Luca Weiss <luca.weiss@xxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 6 +++---
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index d7c9edff19f7..ef43af39569c 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -529,13 +529,13 @@ qupv3_id_1: geniqup@9c0000 {
ranges;
status = "disabled";
- uart2: serial@98c000 {
+ uart9: serial@98c000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x98c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_uart2_default>;
+ pinctrl-0 = <&qup_uart9_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -974,7 +974,7 @@ tlmm: pinctrl@f100000 {
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 157>;
- qup_uart2_default: qup-uart2-default {
+ qup_uart9_default: qup-uart9-default {
pins = "gpio25", "gpio26";
function = "qup13_f2";
drive-strength = <2>;
diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
index adb6ca2be2a5..67d14bda3797 100644
--- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
+++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
@@ -23,7 +23,7 @@ / {
qcom,board-id = <8 32>;
aliases {
- serial0 = &uart2;
+ serial0 = &uart9;
};
chosen {
@@ -332,7 +332,7 @@ &tlmm {
gpio-reserved-ranges = <13 4>, <56 2>;
};
-&uart2 {
+&uart9 {
status = "okay";
};
--
2.35.1
