LAN966x SoC supports 3 instances of QSPI.
Data and clock of qspi0, qspi1, qspi2 works upto 100Mhz.
Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@xxxxxxxxxxxxx>
---
arch/arm/boot/dts/lan966x.dtsi | 48 ++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
index 7d2869648050..b3c687db0aea 100644
--- a/arch/arm/boot/dts/lan966x.dtsi
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -196,6 +196,54 @@
status = "disabled";
};
+ qspi0: spi@e0804000 {
+ compatible = "microchip,lan966x-qspi";
+ reg = <0xe0804000 0x100>,
+ <0x20000000 0x08000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks GCK_ID_QSPI0>;
+ clock-names = "gclk";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>,
+ <&dma0 AT91_XDMAC_DT_PERID(1)>;
+ dma-names = "rx", "tx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ qspi1: spi@e0054000 {
+ compatible = "microchip,lan966x-qspi";
+ reg = <0xe0054000 0x100>,
+ <0x40000000 0x08000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks GCK_ID_QSPI1>;
+ clock-names = "gclk";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(15)>,
+ <&dma0 AT91_XDMAC_DT_PERID(16)>;
+ dma-names = "rx", "tx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ qspi2: spi@e0834000 {
+ compatible = "microchip,lan966x-qspi";
+ reg = <0xe0834000 0x100>,
+ <0x30000000 0x08000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks GCK_ID_QSPI2>;
+ clock-names = "gclk";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(17)>,
+ <&dma0 AT91_XDMAC_DT_PERID(18)>;
+ dma-names = "rx", "tx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
can0: can@e081c000 {
compatible = "bosch,m_can";
reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
--
2.17.1
