On Wed, Apr 06, 2022 at 09:40:19AM +0200, Clément Léger wrote: > Le Tue, 5 Apr 2022 12:11:51 -0500, > Rob Herring <robh@xxxxxxxxxx> a écrit : > > > On Tue, Apr 5, 2022 at 10:52 AM Clément Léger <clement.leger@xxxxxxxxxxx> wrote: > > > > > > Le Tue, 5 Apr 2022 09:47:20 -0500, > > > Rob Herring <robh@xxxxxxxxxx> a écrit : > > > > > [...] > > > > > > > I also tried loading an overlay from a driver on an ACPI based system. > > > Their patch is (I guess) targeting the specific problem that there is > > > no base DT when using ACPI. However, Mark Brown feedback was not to > > > mix OF and ACPI: > > > > I agree there. I don't think we should use DT bindings in ACPI tables > > which is already happening. In this case, I think what's described by > > ACPI and DT must be completely disjoint. I think that's the case here > > as everything is downstream of the PCIe device. > > Yes, there is no references to the host devices (at least in my case). > > > > > > "That seems like it's opening a can of worms that might be best left > > > closed." > > > > > > But I would be interested to know how the Xilinx guys are doing that > > > on x86/ACPI based system. > > > > They aren't, yet... > > Ok... > > [...] > > > > > > > > > I've told the Xilinx folks the same thing, but I would separate this > > > > into 2 parts. First is just h/w work in a DT based system. Second is > > > > creating a base tree an overlay can be applied to. The first part should > > > > be pretty straightforward. We already have PCI bus bindings. The only > > > > tricky part is getting address translation working from leaf device thru > > > > the PCI bus to host bus, but support for that should all be in place > > > > (given we support ISA buses off of PCI bus). The second part will > > > > require generating PCI DT nodes at runtime. That may be needed for both > > > > DT and ACPI systems as we don't always describe all the PCI hierarchy > > > > in DT. > > > > > > But then, if the driver generate the nodes, it will most probably > > > have to describe the nodes by hardcoding them right ? > > > > No, the kernel already maintains its own tree of devices. You just > > need to use that to generate the tree. That's really not much more > > than nodes with a 'reg' property encoding the device and function > > numbers. > > Just to clarified a point, my PCI device exposes multiple peripherals > behind one single PCI function. Right. I would expect your PCI device DT node to have a 'simple-bus' child node with all those peripherals. And maybe there's other nodes like fixed-clocks, etc. > To be sure I understood what you are suggesting, you propose to create > a DT node from the PCI driver that has been probed dynamically > matching this same PCI device with a 'reg' property. I also think > this would requires to generate some 'pci-ranges' to remap the > downstream devices that are described in the DTBO, finally, load the > overlay to be apply under this newly created node. Is that right ? Right. You'll need to take the BAR address(es) for the device and stick those into 'ranges' to translate offsets to BAR+offset. Rob
