On Fri, Apr 01, 2022 at 11:59:49PM +0200, Krzysztof Kozlowski wrote:
> Convert the Qualcomm Shared Memory State Machine to DT schema.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> ---
> .../bindings/soc/qcom/qcom,smsm.txt | 104 -------------
> .../bindings/soc/qcom/qcom,smsm.yaml | 138 ++++++++++++++++++
> 2 files changed, 138 insertions(+), 104 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt
> create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt
> deleted file mode 100644
> index 2993b5a97dd6..000000000000
> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt
> +++ /dev/null
> @@ -1,104 +0,0 @@
> -Qualcomm Shared Memory State Machine
> -
> -The Shared Memory State Machine facilitates broadcasting of single bit state
> -information between the processors in a Qualcomm SoC. Each processor is
> -assigned 32 bits of state that can be modified. A processor can through a
> -matrix of bitmaps signal subscription of notifications upon changes to a
> -certain bit owned by a certain remote processor.
> -
> -- compatible:
> - Usage: required
> - Value type: <string>
> - Definition: must be one of:
> - "qcom,smsm"
> -
> -- qcom,ipc-N:
> - Usage: required
> - Value type: <prop-encoded-array>
> - Definition: three entries specifying the outgoing ipc bit used for
> - signaling the N:th remote processor
> - - phandle to a syscon node representing the apcs registers
> - - u32 representing offset to the register within the syscon
> - - u32 representing the ipc bit within the register
> -
> -- qcom,local-host:
> - Usage: optional
> - Value type: <u32>
> - Definition: identifier of the local processor in the list of hosts, or
> - in other words specifier of the column in the subscription
> - matrix representing the local processor
> - defaults to host 0
> -
> -- #address-cells:
> - Usage: required
> - Value type: <u32>
> - Definition: must be 1
> -
> -- #size-cells:
> - Usage: required
> - Value type: <u32>
> - Definition: must be 0
> -
> -= SUBNODES
> -Each processor's state bits are described by a subnode of the smsm device node.
> -Nodes can either be flagged as an interrupt-controller to denote a remote
> -processor's state bits or the local processors bits. The node names are not
> -important.
> -
> -- reg:
> - Usage: required
> - Value type: <u32>
> - Definition: specifies the offset, in words, of the first bit for this
> - entry
> -
> -- #qcom,smem-state-cells:
> - Usage: required for local entry
> - Value type: <u32>
> - Definition: must be 1 - denotes bit number
> -
> -- interrupt-controller:
> - Usage: required for remote entries
> - Value type: <empty>
> - Definition: marks the entry as a interrupt-controller and the state bits
> - to belong to a remote processor
> -
> -- #interrupt-cells:
> - Usage: required for remote entries
> - Value type: <u32>
> - Definition: must be 2 - denotes bit number and IRQ flags
> -
> -- interrupts:
> - Usage: required for remote entries
> - Value type: <prop-encoded-array>
> - Definition: one entry specifying remote IRQ used by the remote processor
> - to signal changes of its state bits
> -
> -
> -= EXAMPLE
> -The following example shows the SMEM setup for controlling properties of the
> -wireless processor, defined from the 8974 apps processor's point-of-view. It
> -encompasses one outbound entry and the outgoing interrupt for the wireless
> -processor.
> -
> -smsm {
> - compatible = "qcom,smsm";
> -
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - qcom,ipc-3 = <&apcs 8 19>;
> -
> - apps_smsm: apps@0 {
> - reg = <0>;
> -
> - #qcom,smem-state-cells = <1>;
> - };
> -
> - wcnss_smsm: wcnss@7 {
> - reg = <7>;
> - interrupts = <0 144 1>;
> -
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - };
> -};
> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml
> new file mode 100644
> index 000000000000..a40d7fa13325
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml
> @@ -0,0 +1,138 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/qcom/qcom,smsm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Shared Memory State Machine
> +
> +maintainers:
> + - Andy Gross <agross@xxxxxxxxxx>
Like I mentioned elsewhere, I'd drop Andy.
> + - Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
> + - Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> +
> +description:
> + The Shared Memory State Machine facilitates broadcasting of single bit state
> + information between the processors in a Qualcomm SoC. Each processor is
> + assigned 32 bits of state that can be modified. A processor can through a
> + matrix of bitmaps signal subscription of notifications upon changes to a
> + certain bit owned by a certain remote processor.
> +
> +properties:
> + compatible:
> + const: qcom,smsm
> +
> + '#address-cells':
> + const: 1
> +
> + qcom,local-host:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0
> + description:
> + Identifier of the local processor in the list of hosts, or in other words
> + specifier of the column in the subscription matrix representing the local
> + processor.
> +
> + '#size-cells':
> + const: 0
> +
> +patternProperties:
> + "^qcom,ipc-[1-4]$":
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: phandle to a syscon node representing the APCS registers
> + - description: u32 representing offset to the register within the syscon
> + - description: u32 representing the ipc bit within the register
> + description:
> + Three entries specifying the outgoing ipc bit used for signaling the N:th
> + remote processor.
> +
> + "^.*@[0-9a-f]$":
Note that dropping '^.*' is equivalent.
Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
