On 29/03/2022 12:17, Tinghan Shen wrote:
Hi Matthias,
Thanks for your comment.
On Mon, 2022-03-28 at 14:26 +0200, Matthias Brugger wrote:
On 16/02/2022 12:31, Tinghan Shen wrote:
Add basic chip support for mediatek mt8195.
Signed-off-by: Seiya Wang <seiya.wang@xxxxxxxxxxxx>
Signed-off-by: Tinghan Shen <tinghan.shen@xxxxxxxxxxxx>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 161 +++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1049 +++++++++++++++++++
3 files changed, 1211 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 8c1e18032f9f..5da29e7223e4 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -38,4 +38,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-
evb.dts
new file mode 100644
index 000000000000..51633d91d984
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
@@ -0,0 +1,161 @@
[...]
+
+&u2port0 {
+ status = "okay";
+};
+
+&u2port1 {
+ status = "okay";
+};
+
+&u3phy0 {
+ status="okay";
+};
+
+&u3phy1 {
+ status="okay";
+};
+
So we enable phys for xhci but not the device. Are we missing anything to enable
them on the EVB?
after discussed with usb expert, we think that we're missing the xhci nodes.
I'll add xhci nodes at next version.
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pin>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
new file mode 100644
index 000000000000..a363e82f6988
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -0,0 +1,1049 @@
[...]
+
+ clk32k: oscillator-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "clk32k";
I suppose the 32KHz oscillator is really present on the board also not used by
any device (up to now?).
Yes. 32KHz clock is still available on MT8195.
Some modules can choose 32K as clock source depending on requirements.
Thanks for the confirmation.
[...]
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
[...]
+
+ pwrap: pwrap@10024000 {
+ compatible = "mediatek,mt8195-pwrap", "syscon";
+ reg = <0 0x10024000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+ <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
+ clock-names = "spi", "wrap";
Binding mandates resets but not present here. It also mandates two register
regions, but only one is given here.
After discussed with pwrap experts, the pwrap binding is out-of-date for mt8195.
They will send a patch to fix pwrap binding.
If possible can you add the patch fixing the pwrap binding in this series, then
I don't have to search for the dependencies in my inbox. That would be of great
help.
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
+ };
+
+ scp_adsp: clock-controller@10720000 {
+ compatible = "mediatek,mt8195-scp_adsp";
+ reg = <0 0x10720000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
[...]
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x10000>,
+ <0 0x11f50000 0 0x1000>;
Seems to be an oversight when adding support for mt8183-mmc support to the
driver. The binding description is missing the optional host top register base.
Chaotian can you please help to fix this in the binding description.
Ok. I'll fix it at next version.
I'm not sure what you mean. I suppose the way forward is to fix the binding
description, correct?
Thanks,
Matthias
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC0>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
[...]
+
+ xhci3: usb@112b0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112b0000 0 0x1000>,
+ <0 0x112b3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port3 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
+ <&topckgen CLK_TOP_SSUSB_P3_REF>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "xhci_ck";
+ /* This controller is connected with a BT device.
+ * Disable usb2 lpm to prevent konwn issues.
+ */
+ usb2-lpm-disable;
My understanding is, that this depends on the board and not the SoC. Which means
usb2-lpm-disable should go into any board that has a BT device connected to the
xhci device (I don't see any active xhci node in mt8195-evb so far).
Ok. I'll move this property to evb board in a xhci node.
Best regards,
TingHan
Regards,
Matthias
