<snip> > > > > diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml > > > > b/Documentation/devicetree/bindings/serial/pl011.yaml > > > > index 5ea00f8a283d..6c73923dd15e 100644 > > > > --- a/Documentation/devicetree/bindings/serial/pl011.yaml > > > > +++ b/Documentation/devicetree/bindings/serial/pl011.yaml > > > > @@ -24,9 +24,13 @@ select: > > > > > > > > properties: > > > > compatible: > > > > - items: > > > > - - const: arm,pl011 > > > > - - const: arm,primecell > > > > + oneOf: > > > > + - items: > > > > + - const: arm,pl011 > > > > + - const: arm,primecell > > > > + - items: > > > > + - const: arm,pl011 > > > > + - const: arm,xlnx-uart # xilinx uart as platform device > > > > > > 'arm,primecell' means the block has ID registers. Are you saying > > > this implementation doesn't? > > > > The ID registers do not have any Xilinx specific identifiers. > > However there are differences like 32-bit access. > > Hope that the current approach is fine with you. Could you please guide how to go about it. > > Thanks > > > > > > > > > > > reg: > > > > maxItems: 1 > > > > -- > > > > 2.25.1 > > > > > > > >
