The CSR GSD4t is a CSR product using the SiRFstarIV core, and
the CSR CSRG05TA03-ICJE-R is a CSR product using the SiRFstarV
core.
These chips have a SRESETN line that can be pulled low to hard
reset the chip and in some designs this is connected to a GPIO,
so add this as an optional property.
Update the example with a reset line so users see that it need
to be tagged as active low.
Cc: devicetree@xxxxxxxxxxxxxxx
Cc: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
Signed-off-by: Linus Walleij <linus.walleij@xxxxxxxxxx>
---
ChangeLog v1->v2:
- Add maxItems: 1 to the reset-gpios
---
Documentation/devicetree/bindings/gnss/sirfstar.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/gnss/sirfstar.yaml b/Documentation/devicetree/bindings/gnss/sirfstar.yaml
index 9f80add3e61b..f3d8902dca04 100644
--- a/Documentation/devicetree/bindings/gnss/sirfstar.yaml
+++ b/Documentation/devicetree/bindings/gnss/sirfstar.yaml
@@ -25,6 +25,8 @@ description:
properties:
compatible:
enum:
+ - csr,gsd4t
+ - csr,csrg05ta03-icje-r
- fastrax,uc430
- linx,r4
- wi2wi,w2sg0004
@@ -39,6 +41,11 @@ properties:
description:
Main voltage regulator, pin names such as 3V3_IN, VCC, VDD.
+ reset-gpios:
+ maxItems: 1
+ description: An optional active low reset line, should be flagged with
+ GPIO_ACTIVE_LOW.
+
timepulse-gpios:
description: Comes with pin names such as 1PPS or TM
@@ -64,6 +71,7 @@ examples:
gnss {
compatible = "wi2wi,w2sg0084i";
vcc-supply = <&gnss_vcc_reg>;
+ reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
sirf,onoff-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
sirf,wakeup-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
current-speed = <38400>;
--
2.35.1
