Add Sunplus SoC SP7021 PWM Driver Signed-off-by: Hammer Hsieh <hammerh0314@xxxxxxxxx> --- Changes in v3: - Addressed all comments from Uwe Kleine-König. MAINTAINERS | 1 + drivers/pwm/Kconfig | 11 +++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sunplus.c | 232 ++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 245 insertions(+) create mode 100644 drivers/pwm/pwm-sunplus.c diff --git a/MAINTAINERS b/MAINTAINERS index e1cb7eb..6644bae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18535,6 +18535,7 @@ SUNPLUS PWM DRIVER M: Hammer Hsieh <hammerh0314@xxxxxxxxx> S: Maintained F: Documentation/devicetree/bindings/pwm/sunplus,sp7021-pwm.yaml +F: drivers/pwm/pwm-sunplus.c SUNPLUS RTC DRIVER M: Vincent Shih <vincent.sunplus@xxxxxxxxx> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 21e3b05..54cfb50 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -572,6 +572,17 @@ config PWM_SUN4I To compile this driver as a module, choose M here: the module will be called pwm-sun4i. +config PWM_SUNPLUS + tristate "Sunplus PWM support" + depends on ARCH_SUNPLUS || COMPILE_TEST + depends on HAS_IOMEM && OF + help + Generic PWM framework driver for the PWM controller on + Sunplus SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-sunplus. + config PWM_TEGRA tristate "NVIDIA Tegra PWM support" depends on ARCH_TEGRA || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 708840b..be58616 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_PWM_STM32) += pwm-stm32.o obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o +obj-$(CONFIG_PWM_SUNPLUS) += pwm-sunplus.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o diff --git a/drivers/pwm/pwm-sunplus.c b/drivers/pwm/pwm-sunplus.c new file mode 100644 index 0000000..b6ab077 --- /dev/null +++ b/drivers/pwm/pwm-sunplus.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PWM device driver for SUNPLUS SP7021 SoC + * + * Links: + * Reference Manual: + * https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview + * + * Reference Manual(PWM module): + * https://sunplus.atlassian.net/wiki/spaces/doc/pages/461144198/12.+Pulse+Width+Modulation+PWM + * + * Limitations: + * - Only supports normal polarity. + * - It output low when PWM channel disabled. + * - When the parameters change, current running period will not be completed + * and run new settings immediately. + * - In .apply() PWM output need to write register FREQ and DUTY. When first write FREQ + * done and not yet write DUTY, it has short timing gap use new FREQ and old DUTY. + * + * Author: Hammer Hsieh <hammerh0314@xxxxxxxxx> + */ +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> + +#define SP7021_PWM_CONTROL0 0x000 +#define SP7021_PWM_CONTROL1 0x004 +#define SP7021_PWM_FREQ(ch) (0x008 + 4 * (ch)) +#define SP7021_PWM_DUTY(ch) (0x018 + 4 * (ch)) +#define SP7021_PWM_FREQ_MAX GENMASK(15, 0) +#define SP7021_PWM_DUTY_MAX GENMASK(7, 0) +#define SP7021_PWM_CONTROL_EN(ch) BIT(ch) + +#define SP7021_PWM_NUM 4 +#define SP7021_PWM_BYPASS_BIT_SHIFT 8 +#define SP7021_PWM_DD_SEL_BIT_SHIFT 8 +#define SP7021_PWM_FREQ_SCALER 256 + +struct sunplus_pwm { + struct pwm_chip chip; + void __iomem *base; + struct clk *clk; +}; + +static inline struct sunplus_pwm *to_sunplus_pwm(struct pwm_chip *chip) +{ + return container_of(chip, struct sunplus_pwm, chip); +} + +static int sunplus_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct sunplus_pwm *priv = to_sunplus_pwm(chip); + u32 dd_freq, duty, control0, control1; + u64 max_period, period_ns, duty_ns, clk_rate; + + if (state->polarity != pwm->state.polarity) + return -EINVAL; + + if (!state->enabled) { + /* disable pwm channel output */ + control0 = readl(priv->base + SP7021_PWM_CONTROL0); + control0 &= ~SP7021_PWM_CONTROL_EN(pwm->hwpwm); + writel(control0, priv->base + SP7021_PWM_CONTROL0); + /* disable pwm channel clk source */ + control1 = readl(priv->base + SP7021_PWM_CONTROL1); + control1 &= ~SP7021_PWM_CONTROL_EN(pwm->hwpwm); + writel(control1, priv->base + SP7021_PWM_CONTROL1); + return 0; + } + + clk_rate = clk_get_rate(priv->clk); + /* + * SP7021_PWM_FREQ_MAX 16 bits, SP7021_PWM_FREQ_SCALER 8 bits + * NSEC_PER_SEC 30 bits, won't overflow. + */ + max_period = mul_u64_u64_div_u64(SP7021_PWM_FREQ_MAX, (u64)SP7021_PWM_FREQ_SCALER + * NSEC_PER_SEC, clk_rate); + + period_ns = min(state->period, max_period); + duty_ns = state->duty_cycle; + + /* + * cal pwm freq and check value under range + * clk_rate 202.5MHz 28 bits, period_ns max 82849185 27 bits, won't overflow. + */ + dd_freq = mul_u64_u64_div_u64(clk_rate, period_ns, (u64)SP7021_PWM_FREQ_SCALER + * NSEC_PER_SEC); + + if (dd_freq == 0) + return -EINVAL; + + if (dd_freq > SP7021_PWM_FREQ_MAX) + dd_freq = SP7021_PWM_FREQ_MAX; + + writel(dd_freq, priv->base + SP7021_PWM_FREQ(pwm->hwpwm)); + + /* cal and set pwm duty */ + control0 = readl(priv->base + SP7021_PWM_CONTROL0); + control0 |= SP7021_PWM_CONTROL_EN(pwm->hwpwm); + control1 = readl(priv->base + SP7021_PWM_CONTROL1); + control1 |= SP7021_PWM_CONTROL_EN(pwm->hwpwm); + if (duty_ns == period_ns) { + /* PWM channel output = high */ + control0 |= SP7021_PWM_CONTROL_EN(pwm->hwpwm + SP7021_PWM_BYPASS_BIT_SHIFT); + duty = SP7021_PWM_DUTY_MAX; + } else { + control0 &= ~SP7021_PWM_CONTROL_EN(pwm->hwpwm + SP7021_PWM_BYPASS_BIT_SHIFT); + /* + * duty_ns <= period_ns 27 bits, SP7021_PWM_FREQ_SCALER 8 bits + * won't overflow. + */ + duty = mul_u64_u64_div_u64(duty_ns, (u64)SP7021_PWM_FREQ_SCALER, + period_ns); + duty |= (pwm->hwpwm << SP7021_PWM_DD_SEL_BIT_SHIFT); + } + writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); + writel(control1, priv->base + SP7021_PWM_CONTROL1); + writel(control0, priv->base + SP7021_PWM_CONTROL0); + + return 0; +} + +static void sunplus_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct sunplus_pwm *priv = to_sunplus_pwm(chip); + u32 control0, freq, duty; + u64 clk_rate; + + control0 = readl(priv->base + SP7021_PWM_CONTROL0); + + if (control0 & BIT(pwm->hwpwm)) { + clk_rate = clk_get_rate(priv->clk); + freq = readl(priv->base + SP7021_PWM_FREQ(pwm->hwpwm)); + duty = readl(priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); + duty &= ~GENMASK(9, 8); + /* + * freq 16 bits, SP7021_PWM_FREQ_SCALER 8 bits + * NSEC_PER_SEC 30 bits, won't overflow. + */ + state->period = DIV64_U64_ROUND_UP((u64)freq * (u64)SP7021_PWM_FREQ_SCALER + * NSEC_PER_SEC, clk_rate); + /* + * freq 16 bits, duty 8 bits, NSEC_PER_SEC 30 bits, won't overflow. + */ + state->duty_cycle = DIV64_U64_ROUND_UP((u64)freq * (u64)duty * NSEC_PER_SEC, + clk_rate); + state->enabled = true; + } else { + state->enabled = false; + } + + state->polarity = PWM_POLARITY_NORMAL; +} + +static const struct pwm_ops sunplus_pwm_ops = { + .apply = sunplus_pwm_apply, + .get_state = sunplus_pwm_get_state, + .owner = THIS_MODULE, +}; + +static void sunplus_pwm_clk_release(void *data) +{ + struct clk *clk = data; + + clk_disable_unprepare(clk); +} + +static int sunplus_pwm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sunplus_pwm *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) + return dev_err_probe(dev, PTR_ERR(priv->clk), + "get pwm clock failed\n"); + + ret = clk_prepare_enable(priv->clk); + if (ret < 0) { + dev_err(dev, "failed to enable clock: %d\n", ret); + return ret; + } + + ret = devm_add_action_or_reset(dev, sunplus_pwm_clk_release, priv->clk); + if (ret < 0) { + dev_err(dev, "failed to release clock: %d\n", ret); + return ret; + } + + priv->chip.dev = dev; + priv->chip.ops = &sunplus_pwm_ops; + priv->chip.npwm = SP7021_PWM_NUM; + + ret = devm_pwmchip_add(dev, &priv->chip); + if (ret < 0) + return dev_err_probe(dev, ret, "Cannot register sunplus PWM\n"); + + return 0; +} + +static const struct of_device_id sunplus_pwm_of_match[] = { + { .compatible = "sunplus,sp7021-pwm", }, + {} +}; +MODULE_DEVICE_TABLE(of, sunplus_pwm_of_match); + +static struct platform_driver sunplus_pwm_driver = { + .probe = sunplus_pwm_probe, + .driver = { + .name = "sunplus-pwm", + .of_match_table = sunplus_pwm_of_match, + }, +}; +module_platform_driver(sunplus_pwm_driver); + +MODULE_DESCRIPTION("Sunplus SoC PWM Driver"); +MODULE_AUTHOR("Hammer Hsieh <hammerh0314@xxxxxxxxx>"); +MODULE_LICENSE("GPL"); -- 2.7.4
