On Thu, 10 Mar 2022 at 17:00, Yann Gautier <yann.gautier@xxxxxxxxxxx> wrote: > > On 3/8/22 11:57, Ulf Hansson wrote: > > Hi Yann, > > > > On Fri, 4 Mar 2022 at 14:52, Yann Gautier <yann.gautier@xxxxxxxxxxx> wrote: > >> > >> On STMicroelectronics variant of PL18x, the DMA Linked Lists are supported > >> starting from revision v2 of the peripheral. But it has limitations, > >> as all the buffers should be aligned on block size (except the last one). > >> But this cannot be guaranteed with SDIO. We should then have a property > >> to disable the support of LLI. > > > > Indeed, the buffer handling with SDIO is somewhat special, which also > > has been discussed several times on LKML before. In principle, we need > > the SDIO func drivers to respect buffer limitations that should be > > specified by the mmc host drivers. Quite similar to what we already > > have for block devices, like ->max_seg_size, ->max_seg, etc, that is > > set per mmc host. > > > > I realize that implementing something like the above requires bigger > > changes, which is why mmc host drivers instead validates the sglists > > and the elements. In some cases that means returning an error code and > > in others it could mean falling back to a non-DMA based I/O mode. > > > > For the stm32_sdmmc variant, it looks like the sglist validation is > > being managed in sdmmc_idma_validate_data() already. Can it be > > extended to cover this case too, rather than using a DT property? > > > > Kind regards > > Uffe > > Hi Ulf, > > OK, I'll check what can be done for this. Patches 1 and 2 can be > dropped, they will be reworked. Okay. > But patch 3 of this series could be taken, as not linked to LLI > management. Should I push it again alone, or could you review it directly? I have some comments/questions on it, but perhaps it makes it easier for people to follow the discussion if it is done separately. So please push it alone, then I will review it. [...] Kind regards Uffe
