The Allwinner F1C100s has three timer instances, each with their own
interrupt line.
Add the missing two interrupts to the DT node, to match the DT binding.
Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
---
arch/arm/boot/dts/suniv-f1c100s.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 43d342eaf661..57f8932ef898 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -105,7 +105,7 @@ uart0_pe_pins: uart0-pe-pins {
timer@1c20c00 {
compatible = "allwinner,suniv-f1c100s-timer";
reg = <0x01c20c00 0x90>;
- interrupts = <13>;
+ interrupts = <13>, <14>, <15>;
clocks = <&osc24M>;
};
--
2.25.1
