Add gce info for display nodes
- It's required to get drivers' CMDQ support
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 3d16cb0b3ea1..70b50aa0a03c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1202,6 +1202,9 @@
mmsys: syscon@14000000 {
compatible = "mediatek,mt8192-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
#clock-cells = <1>;
};
@@ -1210,6 +1213,8 @@
reg = <0 0x14001000 0 0x1000>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+ mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+ <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
};
smi_common: smi@14002000 {
@@ -1251,6 +1256,7 @@
iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
<&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
};
ovl_2l0: ovl@14006000 {
@@ -1261,6 +1267,7 @@
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
<&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
};
rdma0: rdma@14007000 {
@@ -1272,6 +1279,7 @@
mediatek,larb = <&larb0>;
mediatek,rdma-fifo-size = <5120>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
};
color0: color@14009000 {
@@ -1281,6 +1289,7 @@
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
};
ccorr0: ccorr@1400a000 {
@@ -1289,6 +1298,7 @@
interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
};
aal0: aal@1400b000 {
@@ -1298,6 +1308,7 @@
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
};
gamma0: gamma@1400c000 {
@@ -1307,6 +1318,7 @@
interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
postmask0: postmask@1400d000 {
@@ -1316,6 +1328,7 @@
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
};
dither0: dither@1400e000 {
@@ -1325,6 +1338,7 @@
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
};
dsi0: dsi@14010000 {
@@ -1349,6 +1363,7 @@
clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
<&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
};
rdma4: rdma@14015000 {
@@ -1359,6 +1374,7 @@
clocks = <&mmsys CLK_MM_DISP_RDMA4>;
iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
mediatek,rdma-fifo-size = <2048>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
};
dpi0: dpi@14016000 {
--
2.18.0
