Fillup the OSTM{0,1,2} stub nodes in RZ/V2L (R9A07G054) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 24 +++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 1207a99bf3fe..50cb2f0e6e73 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -629,18 +629,36 @@
};
ostm0: timer@12801000 {
+ compatible = "renesas,r9a07g054-ostm",
+ "renesas,ostm";
reg = <0x0 0x12801000 0x0 0x400>;
- /* place holder */
+ interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
+ resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
ostm1: timer@12801400 {
+ compatible = "renesas,r9a07g054-ostm",
+ "renesas,ostm";
reg = <0x0 0x12801400 0x0 0x400>;
- /* place holder */
+ interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
+ resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
ostm2: timer@12801800 {
+ compatible = "renesas,r9a07g054-ostm",
+ "renesas,ostm";
reg = <0x0 0x12801800 0x0 0x400>;
- /* place holder */
+ interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
+ resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
+ power-domains = <&cpg>;
+ status = "disabled";
};
};
--
2.17.1
