Fillup the sbc stub node in RZ/V2L (R9A07G054) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index fafb986fe3bc..1207a99bf3fe 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -398,12 +398,20 @@
};
sbc: spi@10060000 {
+ compatible = "renesas,r9a07g054-rpc-if",
+ "renesas,rzg2l-rpc-if";
reg = <0 0x10060000 0 0x10000>,
<0 0x20000000 0 0x10000000>,
<0 0x10070000 0 0x10000>;
+ reg-names = "regs", "dirmap", "wbuf";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
+ <&cpg CPG_MOD R9A07G054_SPI_CLK>;
+ resets = <&cpg R9A07G054_SPI_RST>;
+ power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
- /* place holder */
+ status = "disabled";
};
cpg: clock-controller@11010000 {
--
2.17.1
