The quartz64 model a has support for both the dwc3 otg port and the dwc3
host port. Add the otg power supply and dwc3 nodes to the device tree to
enable support for these.
Signed-off-by: Peter Geis <pgwipeout@xxxxxxxxx>
---
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index dd7f4b9b686b..a911fa1ef955 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -151,6 +151,16 @@ vcc5v0_usb20_host: vcc5v0_usb20_host {
vin-supply = <&vcc5v0_usb>;
};
+ vcc5v0_usb20_otg: vcc5v0_usb20_otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc5v0_usb20_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dcdc_boost>;
+ };
+
vcc3v3_sd: vcc3v3_sd {
compatible = "regulator-fixed";
enable-active-low;
@@ -187,6 +197,10 @@ vcc_wl: vcc_wl {
};
};
+&combphy1 {
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
@@ -672,6 +686,20 @@ &usb_host1_ohci {
status = "okay";
};
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb20_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb20_otg>;
+ status = "okay";
+};
+
&usb2phy1 {
status = "okay";
};
@@ -685,3 +713,12 @@ &usb2phy1_otg {
phy-supply = <&vcc5v0_usb20_host>;
status = "okay";
};
+
+&usbdrd30 {
+ status = "okay";
+};
+
+/* usb3 controller is muxed with sata1 */
+&usbhost30 {
+ status = "okay";
+};
--
2.25.1
