On Tue, Feb 22, 2022 at 05:13:41PM -0600, Rob Herring wrote:
> On Tue, Feb 22, 2022 at 03:26:53PM +0530, shruthi.sanil@xxxxxxxxx wrote:
> > From: Shruthi Sanil <shruthi.sanil@xxxxxxxxx>
> >
> > Add Device Tree bindings for the Timer IP, which can be used as
> > clocksource and clockevent device in the Intel Keem Bay SoC.
...
> > + soc {
> > + #address-cells = <0x2>;
> > + #size-cells = <0x2>;
> > +
> > + gpt@20331000 {
> > + compatible = "intel,keembay-gpt-creg", "simple-mfd";
>
> It looks like you are splitting things based on Linux implementation
> details. Does this h/w block have different combinations of timers and
> counters? If not, then you don't need the child nodes at all. There's
> plenty of h/w blocks that get used as both a clocksource and clockevent.
>
> Maybe I already raised this, but assume I don't remember and this patch
> needs to address any questions I already asked.
I dunno if I mentioned that hardware seems to have 5 or so devices behind
the block, so ideally it should be one device node that represents the global
register spaces and several children nodes.
However, I am not familiar with the established practices in DT world, but
above seems to me the right thing to do since it describes the hardware as
is (without any linuxisms).
> > + reg = <0x0 0x20331000 0x0 0xc>;
> > + ranges = <0x0 0x0 0x20330000 0xF0>;
> > + #address-cells = <0x1>;
> > + #size-cells = <0x1>;
> > +
> > + counter@e8 {
> > + compatible = "intel,keembay-counter";
> > + reg = <0xe8 0x8>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + };
> > +
> > + timer@30 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x30 0xc>;
> > + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + };
> > + };
> > + };
--
With Best Regards,
Andy Shevchenko
