On Tue, Feb 22, 2022 at 03:26:53PM +0530, shruthi.sanil@xxxxxxxxx wrote: > From: Shruthi Sanil <shruthi.sanil@xxxxxxxxx> > > Add Device Tree bindings for the Timer IP, which can be used as > clocksource and clockevent device in the Intel Keem Bay SoC. > > Reviewed-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxx> > Signed-off-by: Shruthi Sanil <shruthi.sanil@xxxxxxxxx> > --- > .../bindings/timer/intel,keembay-timer.yaml | 128 ++++++++++++++++++ > 1 file changed, 128 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > new file mode 100644 > index 000000000000..9e6d46ecc2dc > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > @@ -0,0 +1,128 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Intel Keem Bay SoC Timers > + > +maintainers: > + - Shruthi Sanil <shruthi.sanil@xxxxxxxxx> > + > +description: | > + The Intel Keem Bay timer driver supports 1 free running counter and 8 timers. Bindings describe the h/w, not what drivers support. > + Each timer is capable of generating inividual interrupt. > + Both the features are enabled through the timer general config register. > + > + The parent node represents the common general configuration details and > + the child nodes represents the counter and timers. > + > +properties: > + compatible: > + oneOf: > + - items: Don't need oneOf with only 1 entry. > + - enum: > + - intel,keembay-gpt-creg > + - const: simple-mfd > + > + reg: > + description: General configuration register address and length. > + maxItems: 1 > + > + ranges: true > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 1 > + > +required: > + - compatible > + - reg > + - ranges > + - "#address-cells" > + - "#size-cells" > + > +patternProperties: > + "^counter@[0-9a-f]+$": > + description: Properties for Intel Keem Bay counter. > + type: object > + properties: > + compatible: > + oneOf: Don't need oneOf. > + - items: > + - enum: > + - intel,keembay-counter > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + required: > + - compatible > + - reg > + - clocks > + > + "^timer@[0-9a-f]+$": > + description: Properties for Intel Keem Bay timer > + type: object > + properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - intel,keembay-timer > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + required: > + - compatible > + - reg > + - interrupts > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #define KEEM_BAY_A53_TIM > + > + soc { > + #address-cells = <0x2>; > + #size-cells = <0x2>; > + > + gpt@20331000 { > + compatible = "intel,keembay-gpt-creg", "simple-mfd"; It looks like you are splitting things based on Linux implementation details. Does this h/w block have different combinations of timers and counters? If not, then you don't need the child nodes at all. There's plenty of h/w blocks that get used as both a clocksource and clockevent. Maybe I already raised this, but assume I don't remember and this patch needs to address any questions I already asked. > + reg = <0x0 0x20331000 0x0 0xc>; > + ranges = <0x0 0x0 0x20330000 0xF0>; > + #address-cells = <0x1>; > + #size-cells = <0x1>; > + > + counter@e8 { > + compatible = "intel,keembay-counter"; > + reg = <0xe8 0x8>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + }; > + > + timer@30 { > + compatible = "intel,keembay-timer"; > + reg = <0x30 0xc>; > + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + }; > + }; > + }; > + > +... > -- > 2.17.1 > >
